Texas Instruments TMS320C6A816 Series Technical Reference Manual page 85

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19-39. Supplementary Status Register (SSR) Field Descriptions
19-40. BOF Length Register (EBLR) Field Descriptions
19-41. Module Version Register (MVR) Field Descriptions
19-42. System Configuration Register (SYSC) Field Descriptions
19-43. System Status Register (SYSS) Field Descriptions
19-44. Wake-Up Enable Register (WER) Field Descriptions
19-45. Carrier Frequency Prescaler Register (CFPS) Field Descriptions
19-46. Divisor Latches Low Register (DLL) Field Descriptions
19-47. Divisor Latches High Register (DLH) Field Descriptions
19-48. Enhanced Feature Register (EFR) Field Descriptions
19-49. EFR[3:0] Software Flow Control Options
19-50. XON1/ADDR1 Register Field Descriptions
19-51. XON2/ADDR2 Register Field Descriptions
19-52. XOFF1 Register Field Descriptions
19-53. XOFF2 Register Field Descriptions
19-54. Transmit Frame Length Low Register (TXFLL) Field Descriptions
19-55. Transmit Frame Length High Register (TXFLH) Field Descriptions
19-56. Received Frame Length Low Register (RXFLL) Field Descriptions
19-57. Received Frame Length High Register (RXFLH) Field Descriptions
19-58. UART Autobauding Status Register (UASR) Field Descriptions
20-1. USBSS Interface Signals
20-2. PERI_TXCSR Register Bit Configuration for Bulk IN Transactions
20-3. PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions
20-4. PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions
20-5. PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions
20-6. Isochronous OUT Error Handling: Peripheral Mode
20-7. Packet Descriptor Word 0 (PD0) Bit Field Descriptions
20-8. Packet Descriptor Word 1 (PD1) Bit Field Descriptions
20-9. Packet Descriptor Word 2 (PD2) Bit Field Descriptions
20-10. Packet Descriptor Word 3 (PD3) Bit Field Descriptions
20-11. Packet Descriptor Word 4 (PD4) Bit Field Descriptions
20-12. Packet Descriptor Word 5 (PD5) Bit Field Descriptions
20-13. Packet Descriptor Word 6 (PD6) Bit Field Descriptions
20-14. Packet Descriptor Word 7 (PD7) Bit Field Descriptions
20-15. Buffer Descriptor Word 0 (BD0) Bit Field Descriptions
20-16. Buffer Descriptor Word 1 (BD1) Bit Field Descriptions
20-17. Buffer Descriptor Word 2 (BD2) Bit Field Descriptions
20-18. Buffer Descriptor Word 3 (BD3) Bit Field Descriptions
20-19. Buffer Descriptor Word 4 (BD4) Bit Field Descriptions
20-20. Buffer Descriptor Word 5 (BD5) Bit Field Descriptions
20-21. Buffer Descriptor Word 6 (BD6) Bit Field Descriptions
20-22. Buffer Descriptor Word 7 (BD7) Bit Field Descriptions
20-23. Teardown Descriptor Word 0 Bit Field Descriptions
20-24. Teardown Descriptor Words 1 to 7 Bit Field Descriptions
20-25. Queue-Endpoint Assignments
20-26. 53 Bytes Test Packet Content
20-27. Subsystem Interrupts
20-28. CPPI DMA Packet Completion Hardware Interrupt Groupings
20-29. Controller Interrupts
SPRUGX9 - 15 April 2011
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