Texas Instruments TMS320C6A816 Series Technical Reference Manual page 201

C6-integra dsp+arm processors
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1.11.2.2 L3 Port Mapping
Each initiator and target core is connected to the L3 interconnect through an NIU. The NIUs act as entry
and exit points to the L3 Network on Chip – converting between the IP's OCP protocol and the NOC's
internal protocol, and also include various programming registers. All ports are single threaded with tags
used to enable pipelined transactions. The SoC interconnect includes:
Initiator Ports:
Monza Host ARM SubSystem (HASS) 64-bit initiator Port 1 (HASS Port 0 is a special case 128-bit
initiator which bypasses the L3.)
C674x™ DSP SubSystem MDMA 128-bit initiator port.
C674x™ DSP Subsystem CFG 32-bit initiator port.
HD Video Processing SubSystem (HD-VPSS) 128-bit initiator Port 0 and Port 1.
MMU 128-bit initiator port.
4 TPTC 128-bit read initiator ports.
4 TPTC 128-bit write initiator ports.
Expansion Slot 0 128-bit initiator port.
CPGMAC0 32-bit initiator port.
CPGMAC1 32-bit initiator port.
SATA 32-bit initiator port.
Media Controller 64-bit initiator port.
PCIe 64-bit initiator port.
Debug Subsystem (DAP) 32-bit initiator port.
Graphics accelerator (SGX530) 128-bit initiator port.
USB 32-bit CPPI DMA initiator port.
USB 32-bit Queue Manager initiator port.
JTAG Interface 32-bit initiator port.
Target Ports:
DMM Tiler0 128-bit target port.
DMM Tiler1 128-bit target port.
C674x™ DSP Subsystem SDMA 128-bit target port.
4 TPTC CFG 32-bit target ports.
TPCC CFG 32-bit target port.
Expansion Slot 0 128-bit target port.
System MMU 128-bit target port.
Graphics accelerator (SGX530) 64-bit target port.
PCIe 64-bit target port.
OCM RAM0 64-bit target port.
OCM RAM1 64-bit target port.
Media Controller 64-bit target port.
2 L4_Fast peripheral 32-bit target ports.
Instrumentation L3 32-bit target port.
2 L4_Slow peripheral 32-bit target ports.
L4 Firewall 32-bit target port.
GPMC 32-bit target port.
McASP0 32-bit target port.
McASP1 32-bit target port.
McASP2 32-bit target port.
McBSP 32-bit target port.
HDMI 32-bit target port.
USB 32-bit target port.
SPRUGX9 – 15 April 2011
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© 2011, Texas Instruments Incorporated
Bus Interconnect
201
Chip Level Resources

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