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MPU Subsystem
1.2.10.2.2 MPU Into Standby Mode
The MPU into standby mode follows the following sequence of operation and is applicable to initial
power-up and wakeup from device Off mode.
1. The ARM core initiates entering into standby via software only (CP15 - WFI).
2. MPU modules requested internally of MPU subsystem to enter idle, after ARM core standby detected.
3. MPU is in standby output asserted for PRCM (all outputs guaranteed to be at reset values).
4. PRCM can now request INTC to enter into idle mode. Acknowledge from INTC goes to PRCM.
NOTE: The INTC SWAKEUP output is a pure hardware signal to PRCM for the status of its IDLE
request and IDLE acknowledge handshake.
NOTE: In debug mode, ICE-Crusher could prevent MPU subsystem from entering into IDLE mode.
1.2.10.2.3 MPU Out Of Standby Mode
The MPU out of standby mode follows the following sequence of operation and is applicable to initial
power-up and wakeup from device Off mode.
1. PRCM must start clocks through DPLL programming.
2. Detect active clocking via status output of DPLL.
3. Initiate an interrupt through the INTC to wake up the ARM core from STANDBYWFI mode.
1.2.10.2.4 MPU Power-On From a Powered-Off State
1. MPU Power On, NEON Power On, Core Power On (INTC) should follow the ordered sequence per
power switch daisy chain to minimize the peaking of current during power-up.
NOTE: The core domain must be on, and reset, before the MPU can be reset.
2. Follow the reset sequence as described in the Basic Power-On Reset section.
1.2.10.3 NEON Power Mode Transition
When NEON power domain transition is configured to Automatic Hardware-supervised mode
(CM_CLKSTCTRL_NEON[1:0] CLKTRCTRL_NEON bits are set to 0x3), it can not transition into idle
unless MPU goes into Standby, because of the Hardware Sleep dependency between NEON and the
MPU domain.
In that case, the MPU domain must also be configured in Automatic Hardware Supervised mode
(CM_CLKSTCTRL_MPU[1:0] CLKTRCTRL_MPU bits must be set to 0x3) for the NEON power domain
transition to happen.
For the complete programming model, see the ARM® Cortex™-A8 Technical Reference Manual.
For more information about ARM cortexA8 please refer the website below:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344c/index.html
108
Chip Level Resources
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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