Texas Instruments TMS320C6A816 Series Technical Reference Manual page 11

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10.2 Architecture
10.2.1 Overview
10.2.2 Clock and Frame Sync Generators
10.2.3 Memory Map
10.2.4 Signal Descriptions
10.2.5 Pin Multiplexing
10.2.6 Transfer Modes
10.2.7 General Architecture
10.2.8 Operation
10.2.9 Reset Considerations
10.2.10 Setup and Initialization
10.2.11 Interrupts
10.2.12 EDMA Event Support
10.2.13 Power Management
10.2.14 Emulation Considerations
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10.3 Registers
10.3.1 Revision Identification Register (REV)
10.3.2 Pin Function Register (PFUNC)
10.3.3 Pin Direction Register (PDIR)
10.3.4 Pin Data Output Register (PDOUT)
10.3.5 Pin Data Input Register (PDIN)
10.3.6 Pin Data Set Register (PDSET)
10.3.7 Pin Data Clear Register (PDCLR)
10.3.8 Global Control Register (GBLCTL)
10.3.9 Audio Mute Control Register (AMUTE)
10.3.10 Digital Loopback Control Register (DLBCTL)
10.3.11 Digital Mode Control Register (DITCTL)
10.3.12 Receiver Global Control Register (RGBLCTL)
10.3.13 Receive Format Unit Bit Mask Register (RMASK)
10.3.14 Receive Bit Stream Format Register (RFMT)
10.3.15 Receive Frame Sync Control Register (AFSRCTL)
10.3.16 Receive Clock Control Register (ACLKRCTL)
10.3.17 Receive High-Frequency Clock Control Register (AHCLKRCTL)
10.3.18 Receive TDM Time Slot Register (RTDM)
10.3.19 Receiver Interrupt Control Register (RINTCTL)
10.3.20 Receiver Status Register (RSTAT)
10.3.21 Current Receive TDM Time Slot Registers (RSLOT)
10.3.22 Receive Clock Check Control Register (RCLKCHK)
10.3.23 Receiver DMA Event Control Register (REVTCTL)
10.3.24 Transmitter Global Control Register (XGBLCTL)
10.3.25 Transmit Format Unit Bit Mask Register (XMASK)
10.3.26 Transmit Bit Stream Format Register (XFMT)
10.3.27 Transmit Frame Sync Control Register (AFSXCTL)
10.3.28 Transmit Clock Control Register (ACLKXCTL)
10.3.29 Transmit High-Frequency Clock Control Register (AHCLKXCTL)
10.3.30 Transmit TDM Time Slot Register (XTDM)
10.3.31 Transmitter Interrupt Control Register (XINTCTL)
10.3.32 Transmitter Status Register (XSTAT)
10.3.33 Current Transmit TDM Time Slot Register (XSLOT)
10.3.34 Transmit Clock Check Control Register (XCLKCHK)
10.3.35 Transmitter DMA Event Control Register (XEVTCTL)
10.3.36 Serializer Control Registers (SRCTLn)
10.3.37 DIT Left Channel Status Registers (DITCSRA0-DITCSRA5)
SPRUGX9 – 15 April 2011
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© 2011, Texas Instruments Incorporated
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