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SGX530 Graphics Subsystem
This is achieved through a multithreaded architecture using two levels of scheduling and data partitioning
enabling zero-overhead task switching.
The SGX subsystem is connected to the L3 interconnect by a 128-bit master and a 32-bit slave interface.
1.5.1.1
POWERVR SGX Main Features
•
2D graphics, 3D graphics, vector graphics, and programming support for GP-GPU functions
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Tile-based architecture
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Universal scalable shader engine ( USSE™) – multithreaded engine incorporating pixel and vertex
shader functionality
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Advanced shader feature set – in excess of Microsoft VS3.0, PS3.0, and OpenGL2.0
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Industry-standard API support – Direct3D Mobile, OpenGL ES 1.1 and 2.0, OpenVG v1.0.1
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Fine-grained task switching, load balancing, and power management
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Advanced geometry direct memory access (DMA) driven operation for minimum CPU interaction
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Programmable high-quality image anti-aliasing
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POWERVR SGX core MMU for address translation from the core virtual address to the external
physical address (up to 4GB address range)
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Fully virtualized memory addressing for OS operation in a unified memory architecture
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Advanced and standard 2D operations [e.g., vector graphics, BLTs (block level transfers), ROPs
(raster operations)]
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32K stride support
1.5.1.2
SGX 3D Features
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Deferred pixel shading
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On-chip tile floating point depth buffer
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8-bit stencil with on-chip tile stencil buffer
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8 parallel depth/stencil tests per clock
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Scissor test
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Texture support:
– Cube map
– Projected textures
– 2D textures
– Nonsquare textures
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Texture formats:
– RGBA 8888, 565, 1555
– Monochromatic 8, 16, 16f, 32f, 32int
– Dual channel, 8:8, 16:16, 16f:16f
– Compressed textures PVR-TC1, PVR-TC2, ETC1
– Programmable support for all YUV formats
•
Resolution support:
– Frame buffer maximum size = 2048 x 2048
– Texture maximum size = 2048 x 2048
•
Texture filtering:
– Bilinear, trilinear, anisotropic
– Independent minimum and maximum control
•
Antialiasing:
– 4x multisampling
– Up to 16x full scene anti-aliasing
– Programmable sample positions
146
Chip Level Resources
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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