Texas Instruments TMS320C6A816 Series Technical Reference Manual page 175

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Table 1-64. Media Controller INTC Interrupt Mapping (continued)
Interrupt Number
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
SPRUGX9 – 15 April 2011
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Preliminary
Event Interrupt Source
UARTINT2
GPIOINT0A
GPIOINT0B
Reserved Reserved
USBSSINT
USBINT0
USBINT1
Reserved Reserved
MBINTA
MBINTB
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
SMRFLXINT0 SmartReflex0
DSSINT
DSSINT
EDMAINTA
EDMAINTB
MACRXTHR0 CPGMAC0
MACRXINT0 CPGMAC0
MACTXINT0 CPGMAC0
MACMISC0 CPGMAC0
MACRXTHR1 CPGMAC1
MACRXINT1 CPGMAC1
MACTXINT1 CPGMAC1
MACMISC1 CPGMAC1
GPIOINT1A
GPIOINT1B
SDINT
SPIINT
Reserved Reserved
Reserved Reserved
SMRFLXINT1 SmartReflex1
Reserved Reserved
© 2011, Texas Instruments Incorporated
Description
UART2 UART/IrDA 2 interrupt
GPIO 0 GPIO 0 interrupt 1
GPIO 0 GPIO 0 interrupt 2
USBSS Queue MGR or CPPI Completion interrupt
USBSS RX/TX DMA, Endpoint ready/error, or
USB0 interrupt
USBSS RX/TX DMA, Endpoint ready/error, or
USB1 interrupt
Mailbox Mailbox Interrupt
Mailbox Mailbox Interrupt
SVT SmartReflex interrupt level version
DSS DSS interrupt
DSS DSS interrupt
TPCC Region 4 DMA completion
TPCC Region 5 DMA completion
CPGMAC0 Receive threshold interrupt
CPGMAC0 Receive pending interrupt
CPGMAC0 Transmit pending interrupt
CPGMAC0 Stat, Host, MDIO LINKINT or
MDIO USERINT
CPGMAC1 Receive threshold interrupt
CPGMAC1 Receive pending interrupt
CPGMAC1 Transmit pending interrupt
CPGMAC1 Stat, Host, MDIO LINKINT or
MDIO USERINT
GPIO 1 GPIO 1 interrupt 1
GPIO 1 GPIO 1 interrupt 2
SD/SDIO SDIO interrupt
McSPI SPI Interrupt
HVT SmartReflex interrupt level version
Device Interrupts
175
Chip Level Resources