Table of Contents
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20.9.1 USBSS Registers
20.9.2 USB0 and USB1 Controller Registers
20.9.3 CPPI DMA Controller Registers
20.9.4 CPPI DMA Scheduler Registers
20.9.5 CPPI DMA Queue Manager Registers
20.9.6 USB Mentor Core Registers
20.9.7 FIFOs
20.9.8 USB Related Clock/PHY Control Registers
21
ROM Code Memory and Peripheral Booting
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21.1
Introduction
21.1.1 Device Types
21.1.2 Acronyms and Naming Conventions
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21.2
Overview
21.2.1 Architecture
21.2.2 Functionality
21.3
Memory Map
21.3.1 Public ROM Memory Map
21.3.2 Public RAM Memory Map
21.4
Startup and Configuration
21.4.1 ROM Code Start-up
21.4.2 CPU State at Public Startup
21.4.3 Clocking Configuration
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21.5
Booting
21.5.1 Overview
21.5.2 Device List
21.6
Fast Internal Booting
21.6.1 Overview
21.6.2 External Booting
21.7
Memory Booting
21.7.1 Overview
21.7.2 XIP Memory
21.7.3 NAND
21.7.4 SD Cards
21.8
Peripheral Booting
21.8.1 Overview
21.8.2 Boot Image Location and Size
21.8.3 Peripheral Boot Procedure Overview
21.8.4 Ethernet Boot Procedure
21.8.5 PCIe Boot Procedure
21.8.6 UART Boot Procedure
21.9
Image Format
21.9.1 Overview
21.9.2 Table of Contents
21.10 Image Execution
21.10.1 Overview
21.10.2 Execution
21.11 Services for HLOS Support
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21.12 Tracing
SPRUGX9 – 15 April 2011
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Preliminary
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© 2011, Texas Instruments Incorporated
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