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1.10.3.1.6 Initializing and Enabling MAINPLL from Power Down Mode
If the MAINPLL is powered down(MAIN_PLLEN bit in MAINPLL_CTRL is cleared to 0), perform the
following procedure to initialize the MAINPLL:
1. Set MAIN_BP bit in MAINPLL_CTRL to 1 to put MAINPLL Bypass mode.
2. Set MAIN_PLLEN bit in MAINPLL_CTRL to 1 to bring MAINPLL out of power-down mode.
3. Clear PWD_CLK1, PWD_CLK2, ...,PWD_CLK7 bits in MAINPLL_PWD to 0 to bring individual output
clocks of MAINPLL out of power-down mode.
4. Set or Clear MAIN_LOC_CTL bit field of MAINPLL_CTRL to select MAINPLL lock output
polarity(MAIN_LOCK bit field of MAINPLL_CTRL).
5. Program the required pre-divider and mutlipler values in bit fields MAIN_P and MAIN_N of
MAINPLL_CTRL respectively.
6. If necessary, program MAIN_INTFREQx and MAIN_FRACFREQx bit field of MAINPLL_FREQx and
set MAIN_LDFREQx bit field to 1 of MAINPLL_FREQx to load integer and fraction values into Main
Synthesizer x respectively.
7. If necessary, program MAIN_MDIVx bit field of MAINPLL_DIVx and set MAIN_LDMDIVx bit field to 1 of
MAINPLL_DIVx to load the Post Divider into Main Synthesizer x respectively.
8. Wait for PLL to Lock: Poll for MAIN_LOCK bit field of MAINPLL_CTRL to become 1 if MAIN_LOC_CTL
bit field of MAINPLL_CTRL was set to 0
else Poll for MAIN_LOCK bit field of MAINPLL_CTRL to become 0 if MAIN_LOC_CTL bit field of
MAINPLL_CTRL was set to 1
9. If MAINPLL is locked in step 8, then clear the MAIN_BP bit in MAINPLL_CTRL to 0 to bring MAINPLL
out from bypass mode.
Where x = 1, 2, 3, 4, 5 Flying Adder Synthesizer.
1.10.3.1.7 Changing MAINPLL Multiplier
If the MAINPLL is not powered down(MAIN_PLLEN bit in MAINPLL_CTRL is set to 1), perform the
following procedure to initialize the MAINPLL:
1. Set MAIN_BP bit in MAINPLL_CTRL to 1 to put MAINPLL Bypass mode.
2. Clear PWD_CLK1, PWD_CLK2, ...,PWD_CLK7 bits in MAINPLL_PWD to 0 to bring individual output
clocks of MAINPLL out of power-down mode.
3. Set or Clear MAIN_LOC_CTL bit field of MAINPLL_CTRL to select MAINPLL lock output
polarity(MAIN_LOCK bit field of MAINPLL_CTRL).
4. Program the required pre-divider and mutlipler values in bit fields MAIN_P and MAIN_N of
MAINPLL_CTRL respectively.
5. If necessary, program MAIN_INTFREQx and MAIN_FRACFREQx bit field of MAINPLL_FREQx and
set MAIN_LDFREQx bit field to 1 of MAINPLL_FREQx to load integer and fraction values into Main
Synthesizer x respectively.
6. If necessary, program MAIN_MDIVx bit field of MAINPLL_DIVx and set MAIN_LDMDIVx bit field to 1 of
MAINPLL_DIVx to load the Post Divider into Main Synthesizer x respectively.
7. Wait for PLL to Lock: Poll for MAIN_LOCK bit field of MAINPLL_CTRL to become 1 if MAIN_LOC_CTL
bit field of MAINPLL_CTRL was set to 0
else Poll for MAIN_LOCK bit field of MAINPLL_CTRL to become 0 if MAIN_LOC_CTL bit field of
MAINPLL_CTRL was set to 1
8. If MAINPLL is locked in step 7, then clear the MAIN_BP bit in MAINPLL_CTRL to 0 to bring MAINPLL
out from bypass mode.
Where x = 1, 2, 3, 4, 5 Flying Adder Synthesizer.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Device Clocking and Flying Adder PLL
Chip Level Resources
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