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An event stops generating interrupt requests when a logical 1 is written to the corresponding mask bit in
the MAILBOX_IRQENABLE_CLR_u register. Events are only reported in the appropriate
MAILBOX_IRQSTATUS_RAW_u register.
In case of the MAILBOX_IRQSTATUS_RAW_u register, the event is reported in the corresponding bit
even if the interrupt request generation is disabled for this event.
1.13.3.5 Assignment
1.13.3.5.1 Description
To assign a receiver to a mailbox, set the new message interrupt enable bit corresponding to the desired
mailbox in the MAILBOX_IRQENABLE_SET_u register. The receiver reads the MAILBOX_MESSAGE_m
register to retrieve a message from the mailbox.
An alternate method for the receiver that does not use the interrupts is to poll the
MAILBOX_FIFOSTATUS_m and/or MAILBOX_MSGSTATUS_m registers to know when to send or
retrieve a message to or from the mailbox. This method does not require assigning a receiver to a
mailbox. Because this method does not include the explicit assignment of the mailbox, the software must
avoid having multiple receivers use the same mailbox, which can result in incoherency.
To assign a sender to a mailbox, set the queue-not-full interrupt enable bit of the desired mailbox in the
MAILBOX_IRQENABLE_SET_u register, where u is the number of the sending user. However, direct
allocation of a mailbox to a sender is not recommended because it can cause the sending processor to be
constantly interrupted.
It is recommended that register polling be used to:
•
Check the status of either the MAILBOX_FIFOSTATUS_m or MAILBOX_MSGSTATUS_m registers
•
Write the message to the corresponding MAILBOX_MESSAGE_m register, if space is available
The sender might use the queue-not-full interrupt when the initial mailbox status check indicates the
mailbox is full. In this case, the sender can enable the queue-not-full interrupt for its mailbox in the
appropriate MAILBOX_IRQENABLE_SET_u register. This allows the sender to be notified by interrupt
only when a FIFO queue has at least one available entry.
Reading the MAILBOX_IRQSTATUS_CLR_u register determines the status of the new message and the
queue-not-full interrupts for a particular user. Writing 1 to the corresponding bit in the
MAILBOX_IRQSTATUS_CLR_u register acknowledges, and subsequently clears, an interrupt.
Assigning multiple senders or multiple receivers to the same mailbox is not
recommended.
1.13.3.6 Sending and Receiving Messages
1.13.3.6.1 Description
When a 32-bit message is written to the MAILBOX_MESSAGE_m register, the message is appended into
the FIFO queue. This queue holds four messages. If the queue is full, the message is discarded. Queue
overflow can be avoided by first reading the MAILBOX_FIFOSTATUS_m register to check that the
mailbox message queue is not full before writing a new message to it. Reading the
MAILBOX_MESSAGE_m register returns the message at the beginning of the FIFO queue and removes it
from the queue. If the FIFO queue is empty when the MAILBOX_MESSAGE_m register is read, the value
0 is returned. The new message interrupt is asserted when at least one message is in the mailbox
message FIFO queue. To determine the number of messages in the mailbox message FIFO queue, read
the MAILBOX_MSGSTATUS_m register.
SPRUGX9 – 15 April 2011
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