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15.3.11 Alarm Day of the Month Register (ALARM_DAYS_REG)
15.3.12 Alarm Month Register (ALARM_MONTHS_REG)
15.3.13 Alarm Year Register (ALARM_YEARS_REG)
15.3.14 Control Register (CTRL_REG)
15.3.15 Status Register (STATUS_REG)
15.3.16 Interrupt Register (INTERRUPTS_REG)
15.3.17 Compensation (LSB) Register (COMP_LSB_REG)
15.3.18 Compensation (MSB) Register (COMP_MSB_REG)
15.3.19 Oscillator Register (OSC_REG)
15.3.20 Scratch Registers (SCRATCHx_REG)
15.3.21 Kick Registers (KICK0R, KICK1R)
15.3.22 RTC Revision Register (RTC_REVISION)
15.3.23 System Configuration Register (RTC_SYSCONFIG)
15.3.24 Wakeup Enable Register (RTC_IRQWAKEEN)
16
Serial ATA (SATA) Controller
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16.1
Introduction
16.1.1 Purpose of the Peripheral
16.1.2 Features Supported
16.1.3 Features Not Supported
16.1.4 Functional Block Diagram
16.1.5 Industry Standard(s) Compliance
16.1.6 Non-Industry Standard(s) Compliance
16.1.7 Terminology Used in this Document
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16.2
Architecture
16.2.1 Clock Control
16.2.2 Signal Description
16.2.3 DMA
16.2.4 Transport Layer
16.2.5 FIFOs
16.2.6 Link Layer
16.2.7 PHY
16.2.8 Pin Multiplexing
16.2.9 Power Management
16.2.10 Reset
16.2.11 Interfacing to Single and Multiple Devices
16.2.12 Initialization
16.2.13 Interrupt Support
16.2.14 EDMA Event Support
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16.3
Use Cases
16.3.1
General Utilities: Structures and Subroutines Sample Program Uses
16.3.2 Example on Initialization and Spinning Up Device
16.3.3 Example of DMA Write Transfer
16.3.4 Example of DMA Read Transfer
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16.4
Registers
16.4.1 HBA Capabilities Register (CAP)
16.4.2 Global HBA Control Register (GHC)
16.4.3 Interrupt Status Register (IS)
16.4.4 Ports Implemented Register (PI)
16.4.5 AHCI Version Register (VS)
16.4.6 Command Completion Coalescing Control Register (CCC_CTL)
16.4.7 Command Completion Coalescing Ports Register (CCC_PORTS)
16.4.8 BIST Active FIS Register (BISTAFR)
16.4.9 BIST Control Register (BISTCR)
16
Contents
Preliminary
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© 2011, Texas Instruments Incorporated
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SPRUGX9 – 15 April 2011
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