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1.4.4.1.2 Subsequence - Configure a TLB entry
Load the Virtual Address Tag
Protect the TLB entry against flush
Validate the TLB entry
Define the page size
1.4.4.2
Operational Modes Configuration
1.4.4.2.1 Main Sequence - Writing TLB Entries Statically
Writing TLB entries statically avoids the need to write translation tables in memory and is commonly used
for relatively small address spaces. This method ensures that the translation of time-critical data accesses
execute as fast as possible with entries already present in the TLB. These entries must be locked to
prevent them from being overwritten.
Execute software reset
Wait for reset to complete
Enable power saving via automatic interface clock gating
Configure TLB entries
Load the physical Address of the page
Define the endianness of the page (little endian or big
endian)
Select the element size
Define mixed page attribute
Specify the TLB entry you want to write
Load the specified entry in the TLB
Enable multihit fault and TLB miss
Enable memory translations
1.4.4.2.2 Main Sequence - Protecting TLB Entries
The first n TLB entries (with n < total number of TLB entries) can be protected from being overwritten with
new translations. This is useful to ensure that certain commonly used or time-critical translations are
always in the TLB and do not require retrieval using the table walking process.
Locks the TLB entries
SPRUGX9 – 15 April 2011
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Preliminary
Table 1-16. Configure a TLB Entry
Step
Table 1-17. MMU Writing TLB Entries Statically
Step
Table 1-18. Protecting TLB Entries
Step
© 2011, Texas Instruments Incorporated
Registe/Bitfield/Programming Model
MMU_CAM[31:12] VATAG
MMU_CAM[3] P
MMU_CAM[2] V
MMU_CAM[1:0] PAGESIZE
Register/ Bitfield / Programming Model
MMU_SYSCONFIG[1] SOFTRESET
MMU_SYSSTATUS[0] RESETDONE
MMU_SYSCONFIG[0] AUTOIDLE
Refer to table Configure a TLB Entry
MMU_RAM[31:12] PHYSICALADDRESS
MMU_RAM[9] ENDIANNESS
MMU_RAM[8:7] ELEMENTSIZE
MMU_RAM[6] MIXED
MMU_LOCK[8:4] CURRENTVICTIM
MMU_LD_TLB[0] LDTLBITEM
MMU_IRQENABLE[4] MULTIHITFAULT
MMU_IRQENABLE[0] TLBMISS
MMU_CNTL[1] MMUENABLE
Register/Bitfield/Programming Model
MMU_LOCK[14:10] BASEVALUE
System MMU
Value
0x-
0x1
0x1
0x-
Value
0x1
=0x1
0x1
0x-
0x-
0x-
0x-
0x-
0x1
0x1
0x1
0x1
Value
0x-
131
Chip Level Resources
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