Texas Instruments TMS320C6A816 Series Technical Reference Manual page 59

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1-146. ELM_SYNDROME_FRAGMENT_4_i Register Field Descriptions
1-147. ELM_SYNDROME_FRAGMENT_5_i Register Field Descriptions
1-148. ELM_SYNDROME_FRAGMENT_6_i Register Field Descriptions
1-149. ELM_LOCATION_STATUS_i Register Field Descriptions
1-150. ELM_ERROR_LOCATION_0-15_i Registers Field Descriptions
1-151. PLL BOOT Registers
1-152. Control Status Register (CONTROL_STATUS) Field Descriptions
1-153. 5.1.2. Boot Status Register (BOOTSTAT) Field Descriptions
1-154. 5.1.3. DSP Boot Address Register (DSPBOOTADDR) Field Descriptions
1-155. PLL Control Registers
1-156. Main PLL Control Register (MAINPLL_CTRL) Field Descriptions
1-157. Main PLL Powerdown Register (MAINPLL_PWD) Field Descriptions
1-158. Main PLL Frequency 1 Register (MAINPLL_FREQ1) Field Descriptions
1-159. Main PLL Divider 1 Register (MAINPLL_DIV1) Field Descriptions
1-160. Main PLL Frequency 2 Register (MAINPLL_FREQ2) Field Descriptions
1-161. Main PLL Divider 2 Register (MAINPLL_DIV2) Field Descriptions
1-162. Main PLL Frequency 4 Register (MAINPLL_FREQ4) Field Descriptions
1-163. Main PLL Divider 4 Register (MAINPLL_DIV4) Field Descriptions
1-164. Main PLL Frequency 5 Register (MAINPLL_FREQ5) Field Descriptions
1-165. Main PLL Divider 5 Register (MAINPLL_DIV5) Field Descriptions
1-166. Main PLL Divider 6 Register (MAINPLL_DIV6) Field Descriptions
1-167. Main PLL Divider 7 Register (MAINPLL_DIV7) Field Descriptions
1-168. DDR PLL Control Register (DDRPLL_CTRL) Field Descriptions
1-169. DDR PLL Powerdown Register (DDRPLL_PWD) Field Descriptions
1-170. DDR PLL Divider 1 Register (DDRPLL_DIV1) Field Descriptions
1-171. DDR PLL Frequency 2 Register (DDRPLL_FREQ2) Field Descriptions
1-172. DDR PLL Divider 2 Register (DDRPLL_DIV2) Field Descriptions
1-173. DDR PLL Frequency 3 Register (DDRPLL_FREQ3) Field Descriptions
1-174. DDR PLL Divider 3 Register (DDRPLL_DIV3) Field Descriptions
1-175. DDR PLL Frequency 4 Register (DDRPLL_FREQ4) Field Descriptions
1-176. DDR PLL Divider 4 Register (DDRPLL_DIV4) Field Descriptions
1-177. DDR PLL Frequency 5 Register (DDRPLL_FREQ5) Field Descriptions
1-178. DDR PLL Divider 5 Register (DDRPLL_DIV5) Field Descriptions
1-179. Video PLL Control Register (VIDEOPLL_CTRL) Field Descriptions
1-180. Video PLL Powerdown Register (VIDEOPLL_PWD) Field Descriptions
1-181. Video PLL Frequency 1 Register (VIDEOPLL_FREQ1) Field Descriptions
1-182. Video PLL Divider 1 Register (VIDEOPLL_DIV1) Field Descriptions
1-183. Video PLL Frequency 2 Register (VIDEOPLL_FREQ2) Field Descriptions
1-184. Video PLL Divider 2 Register (VIDEOPLL_DIV2) Field Descriptions
1-185. Video PLL Frequency 3 Register (VIDEOPLL_FREQ3) Field Descriptions
1-186. Video PLL Divider 3 Register (VIDEOPLL_DIV3) Field Descriptions
1-187. Audio PLL Control Register (AUDIOPLL_CTRL) Field Descriptions
1-188. Audio PLL Powerdown Register (AUDIOPLL_PWD) Field Descriptions
1-189. Audio PLL Frequency 2 Register (AUDIOPLL_FREQ2) Field Descriptions
1-190. Audio PLL Divider 2 Register (AUDIOPLL_DIV2) Field Descriptions
1-191. Audio PLL Frequency 3 Register (AUDIOPLL_FREQ3) Field Descriptions
1-192. Audio PLL Divider 3 Register (AUDIOPLL_DIV3) Field Descriptions
1-193. Audio PLL Frequency 4 Register (AUDIOPLL_FREQ4) Field Descriptions
1-194. Audio PLL Divider 4 Register (AUDIOPLL_DIV4) Field Descriptions
SPRUGX9 - 15 April 2011
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