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16.4.10 BIST FIS Count Register (BISTFCTR)
16.4.11 BIST Status Register (BISTSR)
16.4.12 BIST DWORD Error Count Register (BISTDECR)
16.4.13 BIST DWORD Error Count Register (TIMER1MS)
16.4.14 Global Parameter 1 Register (GPARAM1R)
16.4.15 Global Parameter 2 Register (GPARAM2R)
16.4.16 Port Parameter Register (PPARAMR)
16.4.17 Test Register (TESTR)
16.4.18 Version Register (VERSIONR)
16.4.19 ID Register (IDR)
16.4.20 Port Command List Base Address Register (P#CLB) (# = 0 or 1)
16.4.21 Port FIS Base Address Register (P#FB) (# = 0 or 1)
16.4.22 Port Interrupt Status Register (P#IS) (# = 0 or 1)
16.4.23 Port Interrupt Enable Register (P#IE) (# = 0 or 1)
16.4.24 Port Command Register (P#CMD) (# = 0 or 1)
16.4.25 Port Task File Data Register (P#TFD) (# = 0 or 1)
16.4.26 Port Signature Register (P#SIG) (# = 0 or 1)
16.4.27 Port Serial ATA Status Register (P#SSTS) (# = 0 or 1)
16.4.28 Port Serial ATA Control Register (P#SCTL) (# = 0 or 1)
16.4.29 Port Serial ATA Error Register (P#SERR) (# = 0 or 1)
16.4.30 Port Serial ATA Active Register (P#SACT) (# = 0 or 1)
16.4.31 Port Command Issue Register (P#CI) (# = 0 or 1)
16.4.32 Port Serial ATA Notification Register (P#SNTF) (# = 0 or 1)
16.4.33 Port DMA Control Register (P#DMACR) (# = 0 or 1)
16.4.34 Port PHY Control Register (P#PHYCR) (# = 0 or 1)
16.4.35 Port PHY Status Register (P#PHYSR) (# = 0 or 1)
16.4.36 Idle Register (IDLE)
16.4.37 PHY Configuration Register 2 (PHYCFGR2)
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17
Timers
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17.1
Introduction
17.1.1 Overview
17.1.2 Features
17.1.3 Functional Block Diagram
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17.2
Architecture
17.2.1 Functional Description
17.2.2 Accessing Registers
17.2.3 Posted Mode Selection
17.2.4 Write Registers Access
17.2.5 Read Registers Access
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17.3
Registers
17.3.1 Identification Register (TIDR)
17.3.2 Timer OCP Configuration Register (TIOCP_CFG)
17.3.3 Timer IRQ EOI Register (IRQ_EOI)
17.3.4 Timer IRQSTATUS Raw Register (IRQSTATUS_RAW)
17.3.5 Timer IRQSTATUS Register (IRQSTATUS)
17.3.6 Timer IRQENABLE Set Register (IRQENABLE_SET)
17.3.7 Timer IRQENABLE Clear Register (IRQENABLE_CLR)
17.3.8 Timer IRQ Wakeup Enable Register (IRQWAKEEN)
17.3.9 Timer Control Register (TCLR)
17.3.10 Timer Counter Register (TCRR)
17.3.11 Timer Load Register (TLDR)
17.3.12 Timer Trigger Register (TTGR)
17.3.13 Timer Write Posted Status Register (TWPS)
SPRUGX9 – 15 April 2011
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© 2011, Texas Instruments Incorporated
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Contents
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