Texas Instruments TMS320C6A816 Series Technical Reference Manual page 83

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16-31. Port Serial ATA Control Register (P#SCTL) Field Descriptions
16-32. Port Serial ATA Error Register (P#SERR) Field Descriptions
16-33. Port Serial ATA Active Register (P#SACT) Field Description
16-34. Port Command Issue Register (P#CI) Field Description
16-35. Port Serial ATA Notification Register (P#SNTF) Field Description
16-36. Port DMA Control Register (P#DMACR) Field Description
16-37. Port PHY Control Register (P#PHYCR) Field Descriptions
16-38. Port PHY Status Register (P#PHYSR) Field Description
16-39. Idle Register (IDLE) Field Description
16-40. PHY Configuration Register 2 (PHYCFGR2) Field Description
17-1. Timer Resolution and Maximum Range
17-2. Prescaler Functionality
17-3. Prescaler Clock Ratios Value
17-4. Value and Corresponding Interrupt Period
17-5. OCP Error Reporting
17-6. Timer Registers
17-7. Identification Register (TIDR) Field Descriptions
17-8. Timer OCP Configuration Register (TIOCP_CFG) Field Descriptions
17-9. Timer IRQ EOI Register (IRQ_EOI) Field Descriptions
17-10. Timer IRQSTATUS Raw Register (IRQSTATUS_RAW) Field Descriptions
17-11. Timer IRQSTATUS Register (IRQSTATUS) Field Descriptions
17-12. Timer IRQENABLE Set Register (IRQENABLE_SET) Field Descriptions
17-13. Timer IRQENABLE Clear Register (IRQENABLE_CLR) Field Descriptions
17-14. Timer IRQ Wakeup Enable Register (IRQWAKEEN) Field Descriptions
17-15. Timer Control Register (TCLR) Field Descriptions
17-16. Timer Counter Register (TCRR) Field Descriptions
17-17. Timer Load Register (TLDR) Field Descriptions
17-18. Timer Trigger Register (TTGR) Field Descriptions
17-19. Timer Write Posted Status Register (TWPS) Field Descriptions
17-20. Timer Match Register (TMAR) Field Descriptions
17-21. Timer Capture Register (TCAR1) Field Descriptions
17-22. Timer Synchronous Interface Control Register (TSICR) Field Descriptions
17-23. Timer Capture Register (TCAR2) Field Descriptions
18-1. Watchdog Timer Events
18-2. Count and Prescaler Default Reset Values
18-3. Prescaler Clock Ratio Values
18-4. Reset Period Examples
18-5. Default Watchdog Timer Reset Periods
18-6. Global Initialization of Surrounding Modules
18-7. Watchdog Timer Module Global Initialization
18-8. Watchdog Timer Basic Configuration
18-9. Disable the Watchdog Timer
18-10. Enable the Watchdog Timer
18-11. Watchdog Timer Registers
18-12. WDT_WIDR Register Field Descriptions
18-13. WDT_WDSC Register Field Descriptions
18-14. WDT_WDST Register Field Descriptions
18-15. WDT_WISR Register Field Descriptions
18-16. WDT_WIER Register Field Descriptions
SPRUGX9 - 15 April 2011
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