Texas Instruments TMS320C6A816 Series Technical Reference Manual page 37

www.ti.com
9-39. Transfer Length Configuration Register (SD_BLK)
9-40. Command Argument Register (SD_ARG)
9-41. Command and Transfer Mode Register (SD_CMD)
9-42. Command Response[31:0] Register (SD_RSP10)
9-43. Command Response[63:32] Register (SD_RSP32)
9-44. Command Response[95:64] Register (SD_RSP54)
9-45. Command Response[127:96] Register (SD_RSP76)
9-46. Data Register (SD_DATA)
9-47. Present State Register (SD_PSTATE)
9-48. Control Register (SD_HCTL)
9-49. SD System Control Register (SD_SYSCTL)
9-50. Interrupt Status Register (SD_STAT)
9-51. Interrupt SD Enable Register (SD_IE)
9-52. Interrupt Signal Enable Register (SD_ISE)
9-53. Auto CMD12 Error Status Register (SD_AC12)
9-54. Capabilities Register (SD_CAPA)
9-55. Maximum Current Capabilities Register (SD_CUR_CAPA)
9-56. Interrupt Signal Enable Register (SD_ISE)
9-57. ADMA Error Status Register (SD_ADMAES)
9-58. ADMA System Address Low Bits (SD_ADMASAL)
9-59. ADMA System Address High Bits Register (SD_ADMASAH)
9-60. Versions Register (SD_REV)
10-1. McASP Block Diagram
10-2. McASP to Parallel 2-Channel DACs
10-3. McASP to 6-Channel DAC and 2-Channel DAC
10-4. McASP to Digital Amplifier
10-5. McASP as Digital Audio Encoder
10-6. McASP as 16 Channel Digital Processor
10-7. TDM Format-6 Channel TDM Example
10-8. TDM Format Bit Delays from Frame Sync
10-9. Inter-Integrated Sound (I2S) Format
10-10. Biphase-Mark Code (BMC)
10-11. S/PDIF Subframe Format
10-12. S/PDIF Frame Format
10-13. Definition of Bit, Word, and Slot
10-14. Bit Order and Word Alignment Within a Slot Examples
10-15. Definition of Frame and Frame Sync Width
10-16. Transmit Clock Generator Block Diagram
10-17. Receive Clock Generator Block Diagram
10-18. Frame Sync Generator Block Diagram
10-19. Burst Frame Sync Mode
10-20. Transmit DMA Event (AXEVT) Generation in TDM Time Slots
10-21. Individual Serializer and Connections Within McASP
10-22. Receive Format Unit
10-23. Transmit Format Unit
10-24. McASP I/O Pin Control Block Diagram
10-25. Processor Service Time Upon Transmit DMA Event (AXEVT)
10-26. Processor Service Time Upon Receive DMA Event (AREVT)
10-27. McASP Audio FIFO (AFIFO) Block Diagram
SPRUGX9 - 15 April 2011
Submit Documentation Feedback
Preliminary
............................................................................
..............................................................................................
................................................................................
...........................................................................................
.........................................................................
.................................................................................
................................................................................
...........................................................................
....................................................................
....................................................................................
.........................................................................
.......................................................................
.........................................................................................
................................................................................................
.................................................................................
...................................................................
............................................................................................
....................................................................................
...........................................................................
.............................................................................
..........................................................................
.................................................................................
...........................................................................................
.............................................................................................
.................................................................................................
......................................................................................
.........................................................................
...........................................................................
...........................................................................
..............................................................................
...............................................................................................
...................................................................................................
...................................................................................................
..............................................................................
.......................................................................
© 2011, Texas Instruments Incorporated
..................................................................
................................................................
..................................................................
.................................................................
.................................................................
...............................................................
......................................................
................................................................
....................................................
...........................................................
..................................................
.............................................................
...................................................
...................................................
974
975
975
979
979
980
980
981
982
985
988
990
995
998
1001
1002
1004
1005
1007
1008
1008
1009
1014
1015
1015
1016
1016
1016
1017
1018
1018
1019
1020
1021
1022
1022
1023
1025
1026
1027
1029
1031
1036
1037
1037
1039
1041
1042
1044
37
List of Figures