Texas Instruments TMS320C6A816 Series Technical Reference Manual page 54

20-148. Interrupt Register for Receive Endpoints 1 to 15 (INTRRX)
20-149. Interrupt Enable Register for INTRTX (INTRTXE)
20-150. Interrupt Enable Register for INTRRX (INTRRXE)
20-151. Interrupt Register for Common USB Interrupts (USBn_INTRUSB)
20-152. Interrupt Enable Register for INTRUSB (USBn_INTRUSBE)
20-153. Frame Number Register (USBn_FRAME)
20-154. Index Register for Selecting the Endpoint Status and Control Registers (USBn_INDEX)
20-155. Register to Enable the USB 2.0 Test Modes (USBn_TESTMODE)
20-156. Maximum Packet Size for Peripheral/Host Transmit Endpoint Register (USBn_TXMAXP)
20-157. Control Status Register for Endpoint 0 in Peripheral Mode (USBn_PERI_CSR0)
20-158. Control Status Register for Endpoint 0 in Host Mode (USBn_HOST_CSR0)
20-159. Control Status Register for Peripheral Transmit Endpoint (USBn_PERI_TXCSR)
20-160. Control Status Register for Host Transmit Endpoint (USBn_HOST_TXCSR)
20-161. Maximum Packet Size for Peripheral/Host Receive Endpoint Register (USBn_RXMAXP)
20-162. Control Status Register for Peripheral Receive Endpoint (USBn_PERI_RXCSR)
20-163. Control Status Register for Host Receive Endpoint (USBn_HOST_RXCSR)
20-164. Count 0 Register (USBn_COUNT0)
20-165. Receive Count Register (USBn_RXCOUNT)
20-166. Type Register (Host mode only) (USBn_HOST_TYPE0)
20-167. Transmit Type Register (Host mode only) (USBn_HOST_TXTYPE)
20-168. NAKLimit0 Register (Host mode only) (USBn_HOST_NAKLIMIT0)
20-169. Transmit Interval Register (Host mode only) (USBn_HOST_TXINTERVAL)
20-170. Receive Type Register (Host mode only) (USBn_HOST_RXTYPE)
20-171. Receive Interval Register (Host mode only) (USBn_HOST_RXINTERVAL)
20-172. Configuration Data Register (USBn_CONFIGDATA)
20-173. Transmit and Receive FIFO Register for Endpoint 0 - 15 (USBn_FIFO0 - USBn_FIFO15)
20-174. Device Control Register (USBn_DEVCTL)
20-175. Transmit Endpoint FIFO Size Register (USBn_TXFIFOSZ)
20-176. Receive Endpoint FIFO Size Register (USBn_RXFIFOSZ)
20-177. Transmit Endpoint FIFO Address Register (USBn_TXFIFOADDR)
20-178. Receive Endpoint FIFO Address Register (USBn_RXFIFOADDR)
20-179. Hardware Version Register (USBn_HWVERS)
20-180. Transmit Function Address Register (USBn_TXFUNCADDRm)
20-181. Transmit Hub Address Register (USBn_TXHUBADDRm)
20-182. Transmit Hub Port (USBn_TXHUBPORTm)
20-183. Receive Function Address Register (USBn_RXFUNCADDRm)
20-184. Receive Hub Address Register (USBn_RXHUBADDRm)
20-185. Receive Hub Port Register (USBn_RXHUBPORTm)
20-186. CM_DEFAULT_L3_SLOW_CLKSTCTRL Register
20-187. USB_CTRL Register
20-188. USBPHY_CTRL0 Register
20-189. USBPHY_CTRL1 Register
21-1. Public ROM Code Architecture
21-2. Public ROM Code Boot Procedure
21-3. ROM Memory Map
21-4. Public RAM Memory Map
21-5. ROM Code Start-up Sequence
21-6. . ROM Code Booting Procedure
21-7. Fast External Boot
54
List of Figures
Preliminary
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© 2011, Texas Instruments Incorporated
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SPRUGX9 - 15 April 2011
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