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4.2.2
Clocking and Reset Strategy
4.2.3
Interrupt Features
4.2.4
General-Purpose Interface Basic Programming Model
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4.3
Registers
4.3.1
GPIO_REVISION Register
4.3.2
GPIO_SYSCONFIG Register
4.3.3
GPIO_EOI Register
4.3.4
GPIO_IRQSTATUS_RAW_n Register
4.3.5
GPIO_IRQSTATUS_n Register
4.3.6
GPIO_IRQSTATUS_SET_n Register
4.3.7
GPIO_IRQSTATUS_CLR_n Register
4.3.8
GPIO_SYSSTATUS Register
4.3.9
GPIO_CTRL Register
4.3.10 GPIO_OE Register
4.3.11 GPIO_DATAIN Register
4.3.12 GPIO_DATAOUT Register
4.3.13 GPIO_LEVELDETECT0 Register
4.3.14 GPIO_LEVELDETECT1 Register
4.3.15 GPIO_RISINGDETECT Register
4.3.16 GPIO_FALLINGDETECT Register
4.3.17 GPIO_DEBOUNCENABLE Register
4.3.18 GPIO_DEBOUNCINGTIME Register
4.3.19 GPIO_CLEARDATAOUT Register
4.3.20 GPIO_SETDATAOUT Register
5
General-Purpose Memory Controller (GPMC)
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5.1
Introduction
5.1.1
Overview
5.1.2
Block Diagram
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5.2
Architecture
5.2.1
GPMC Signals
5.2.2
GPMC Modes
5.2.3
GPMC Integration
5.2.4
GPMC Functional Description
5.3
Basic Programming Model
5.3.1
GPMC High-Level Programming Model Overview
5.3.2
GPMC Initialization
5.3.3
GPMC Configuration in NOR Mode
5.3.4
GPMC Configuration in NAND Mode
5.3.5
Set Memory Access
5.3.6
GPMC Timing Parameters
5.4
Use Cases And Tips
5.4.1
How to Set GPMC Timing Parameters for Typical Accesses
5.4.2
How to Choose a Suitable Memory to Use With the GPMC
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5.5
Registers
5.5.1
GPMC_REVISION
5.5.2
GPMC_SYSCONFIG
5.5.3
GPMC_SYSSTATUS
5.5.4
GPMC_IRQSTATUS
5.5.5
GPMC_IRQENABLE
5.5.6
GPMC_TIMEOUT_CONTROL
5.5.7
GPMC_ERR_ADDRESS
5.5.8
GPMC_ERR_TYPE
5.5.9
GPMC_CONFIG
6
Contents
Preliminary
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© 2011, Texas Instruments Incorporated
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