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C674x DSP Subsystem
1.3.4.3
Unified L1/L2 Cache
The following features are supported by the shared cache design:
•
32-KB L1 unified cache implemented with high-performance bit cell to run at full speed
•
128-KB L2 unified cache implemented with high-density bit cell to optimize area at half speed
•
L1 cache is 32B line size, 4-way set-associative and organized as 16-bank
•
L2 cache is 32B line size and 8-way set associative
•
L1 cache supports snooping
•
L2 cache slave port to support snooping from EDMA accesses
•
Fully pipelined/supports critical-word-first
•
Write-combining
•
Fill and eviction buffers, and hit in fill buffer
•
Dynamic sizing, I/D allocation
•
Prefetch 4 lines/preload N lines
•
Background preload/clean
1.3.4.4
Internal DMA (IDMA) Controller
The IDMA controller performs fast block transfers between any two memory locations local to the C674x
megamodule. Local memory locations are defined as those in Level 1 program (L1P), Level 1 data (L1D),
and Level 2 (L2) memories, or in the external peripheral configuration (CFG) memory. The IDMA cannot
transfer data to or from the internal MMR space. The IDMA is fully described in the TMS320C674x DSP
Megamodule Reference Guide (SPRUFK5).
1.3.4.5
Attribute MMU
The attribute MMU (AMMU) for the shared cache provides the multi-access cache with a region-based
address translation, read/write control, access type control, endiannism, and multilevel cache
maintenance. The MMU is directly connected to the shared cache, and there is a dedicated interface for
pipeline write policy management. L1 policies are queried at the allocation control of the cache, and L2
policies are propagated to the master interface. For flexibility, the MMU can be dedicated to an L1 or an
L2 cache configuration, with or without address translation, or as an L1/L2 cache combination.
The AMMU supports different page sizes: large, medium, and small. The number of large pages, number
of medium pages, etc., is defined at design time. The maximum number of large pages is eight. This
address space includes addresses for all eight regions. However, if the DSP subsystem defines only five
large pages, only the first five addresses are valid.
1.3.4.6
Interrupt Controller (INTC)
The DSP megamodule INTC detects, potentially combines, and routes up to 128 system events (internal
and external) to the DSP CPU interrupt lines.
The DSP CPU has 12 maskable interrupts and one exception input. The INTC includes an interrupt
selector, exception combiner, and event combiner. The interrupt selector allows the routing of any of the
128 system events (or a combination of them) to the 12 maskable interrupts of the DSP CPU, and
software determines the priorities of those system events. To handle potential conflicts, the 12 CPU
interrupts have fixed priorities. The exception combiner allows the combination of any of the 128 system
events to the single exception input of the DSP CPU.
Figure 1-10
shows a block diagram of the DSP INTC megamodule.
For more information on the INTC, see the TMS320C674x DSP Megamodule Reference Guide
(SPRUFK5).
114
Chip Level Resources
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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