Table of Contents
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13.1.6 Industry Standard(s) Compliance Statement
13.1.7 Terminology Used in this Document
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13.2
Architecture
13.2.1 Clock Control
13.2.2 Supported PCIe Transactions
13.2.3 Address Translations
13.2.4 Address Spaces
13.2.5 Bus Mastering
13.2.6 PCIe Loopback
13.2.7 L3 Memory Map
13.2.8 Reset Considerations
13.2.9 Interrupt Support
13.2.10 Firewall
13.2.11 DMA Support
13.2.12 Power Management
13.2.13 Relationship Between Device and Link Power States
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13.3
Use Case
13.3.1 PCIe Root Complex
13.3.2 PCIe End Point
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13.4
Registers
13.4.1 Accessing Read-only Registers in Configuration Space
13.4.2 Accessing EP Application Registers from PCIe RC
13.4.3 Encoding of LTSSM State in DEBUG Registers
13.4.4 Application Registers
13.4.5 Configuration Registers Common to Type 0 and Type 1 Headers
13.4.6 Configuration Type 0 Registers
13.4.7 Configuration Type 1 Registers
13.4.8 PCIe Capability Registers
13.4.9 PCIe Extended Capability Registers
13.4.10 Message Signaled Interrupts Registers
13.4.11 Power Management Capability Registers
13.4.12 Port Logic Registers
14
Power, Reset, and Clock Management (PRCM) Module
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14.1
Introduction
14.1.1 Device Power-Management Architecture Building Blocks
14.1.2 Module-Level Clock Management
14.1.3 Clock Domain
14.1.4 Power Management
14.2
Power Reset Clock Management Overview
14.2.1 Introduction
14.2.2 Interfaces Description
14.2.3 Power Control Interface
14.2.4 FAPLL interface
14.2.5 Device Control Interface
14.2.6 Clocks Interface
14.2.7 Resets Interface
14.2.8 Modules Power Management Control Interface
14.3
Device Modules and Power-Management Attributes List
14.3.1 Active Power Domain Modules Attribute
14.3.2 AlwaysOn Power Domain Modules Attribute
14.3.3 Default Power Domain Modules Attribute
14.3.4 SGX Power Domain Modules Attribute
14.4
Clock Management
14
Contents
Preliminary
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© 2011, Texas Instruments Incorporated
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