Texas Instruments TMS320C6A816 Series Technical Reference Manual page 62

3-25. Ethernet Media Access Controller (EMAC) Registers
3-26. Transmit Identification and Version Register (TXIDVER) Field Descriptions
3-27. Transmit Control Register (TXCONTROL) Field Descriptions
3-28. Transmit Teardown Register (TXTEARDOWN) Field Descriptions
3-29. Receive Identification and Version Register (RXIDVER) Field Descriptions
3-30. Receive Control Register (RXCONTROL) Field Descriptions
3-31. Receive Teardown Register (RXTEARDOWN) Field Descriptions
3-32. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions
3-33. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions
3-34. Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions
3-35. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions
3-36. MAC Input Vector Register (MACINVECTOR) Field Descriptions
3-37. MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions
3-38. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions
3-39. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions
3-40. Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions
3-41. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions
3-42. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions
3-43. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions
3-44. MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions
3-45. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions
3-46. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field
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Descriptions
3-47. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
3-48. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions
3-49. Receive Maximum Length Register (RXMAXLEN) Field Descriptions
3-50. Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions
3-51. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions
3-52. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions
3-53. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions
3-54. MAC Control Register (MACCONTROL) Field Descriptions
3-55. MAC Status Register (MACSTATUS) Field Descriptions
3-56. Emulation Control Register (EMCONTROL) Field Descriptions
3-57. FIFO Control Register (FIFOCONTROL) Field Descriptions
3-58. MAC Configuration Register (MACCONFIG) Field Descriptions
3-59. Soft Reset Register (SOFTRESET) Field Descriptions
3-60. MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions
3-61. MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions
3-62. MAC Hash Address Register 1 (MACHASH1) Field Descriptions
3-63. MAC Hash Address Register 2 (MACHASH2) Field Descriptions
3-64. Back Off Test Register (BOFFTEST) Field Descriptions
3-65. Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions
3-66. Receive Pause Timer Register (RXPAUSE) Field Descriptions
3-67. Transmit Pause Timer Register (TXPAUSE) Field Descriptions
3-68. MAC Address Low Bytes Register (MACADDRLO) Field Descriptions
3-69. MAC Address High Bytes Register (MACADDRHI) Field Descriptions
3-70. MAC Index Register (MACINDEX) Field Descriptions
3-71. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions
3-72. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions
62
List of Tables
Preliminary
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© 2011, Texas Instruments Incorporated
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SPRUGX9 - 15 April 2011
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