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Translation
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1.4.3.1.2 Translation Tables
The translation of virtual to physical addresses is based on entries in translation tables that define the
following properties:
•
Address translation, that is, the correspondence between virtual and physical addresses
•
Size of the memory region the entry translates
•
Endianness, data access size, and the mixed property of this memory region
The virtual addresses index the translation tables. Each virtual address corresponds to exactly one entry
in the translation table.
1.4.3.1.2.1 Translation Table Hierarchy
When developing a table-based address translation scheme, one of the most important design parameters
is the memory page size described by each translation table entry. MMU instances support 4KB and 64KB
pages, a 1MB section, and a 16MB supersection. Using bigger page sizes means a smaller translation
table.
Using a smaller page size greatly increases the efficiency of dynamic memory allocation and
defragmentation. That is why many operating systems (OSs) can operate on memory blocks as small as
4KB; however, the smaller size implies a more complex table structure.
A quick calculation shows that using 4KB memory pages with one translation table would require one
million entries to span the entire 4GB address range. The table itself would be 32MB, a size that is not
feasible.
However, using bigger pages greatly reduces the functionality of the OS memory management.
Implementing a two-level hierarchy reconciles these two requirements. Within this hierarchy, one first-level
translation table describes the translation properties based on 1MB memory regions.
Each of the entries in this first-level translation table can specify the following:
•
The translation properties for a big memory section. This memory section can be either 1MB (section)
or 16MB (supersection). In this case, all translation parameters are specified in the first-level
translation table entry.
SPRUGX9 – 15 April 2011
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Preliminary
Figure 1-13. MMU Address Translation Process
Yes
Translation in TLB
?
No
Yes
Table walking
enabled?
No
Translation
fault
© 2011, Texas Instruments Incorporated
Perform
Translation
translation
Update TLB
Yes
Retrieve
translation: Page table
entry exists?
No
Chip Level Resources
System MMU
result
119
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