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When the constrained image trigger CIT bit is on, component HD output reduces output resolution of
the HD source to have not more than 520,000 pixels per frame (e.g. an image with resolution of 540
vertical lines by 960 horizontal lines for a 16:9 aspect ratio). The HDVPSS reduces horizontal
resolution by dropping every other pixels and scaling up by a factor of two with an interpolator. The
HDVPSS also reduces vertical resolution by either dropping every other line for progressive scan
output or repeating a same field for interlaced scan output. (Update: The HDVPSS decimates both
horizontal and vertical resolution by ½ in each direction using 3-tap decimators and interpolates back
to the original number of pixels and lines using 2-tap average filters.)
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VBI Features
– VBI Closed caption and other data pass-through.
– EIA/CEA-608-B Line 21 Data services – support both SCTE 20 and SCTE 21 standards.
– EIA-708-B Digital Television (DTV) Closed Captioning – support SCTE21/ATSC A/53e standards.
– Reconstruction of lines 10 through 21 of the VBI from a data source available to the host CPU
(video user data DVS706r8 – DVB/SCTE specifications based on PES encoding of VBI data Raw
VBI data, Closed Caption (CC), Teletext (NABTS, WSS), CGMS, VPS, VITC, Gemstar 1x and 2x,
Extended Data Service(XDS), Moji, V-Chip).
– Copy Protection.
– NTSC Analog outputs and Analog component outputs (only for SD modes) – Macrovision version
7.1.
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All analog outputs – CGMS-A on all analog outputs and additional CIT support on HD component
output.
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The device HDVPSS uses 59.94Hz output frame rate for both 59.94 and 60Hz source materials to
maintain same output frame rate on both NTSC and HD outputs.
Video Capture Features
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The HDVPSS supports two independently configurable external video input capture ports.
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Each video input capture port can be operated as one 16/24-bit input channel (with separate Y and
Cb/Cr inputs) or two clock independent 8-bit input channels (with interleaved Y/C data input).
Embedded sync and external sync modes are supported for all input configurations.
Input Data Features
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8 bit input ports.
– A single non-multiplexed CIF/480i/480p/720p/1080i Y/C data.
– Up to 2-stream multiplexed ED (480p) Y/C data.
– Up to 4-stream multiplexed SD (480i) Y/C data.
– Up to 8-stream multiplexed CIF Y/C data.
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16/24 bit input ports.
– A single non-multiplexed CIF/480i/480p/720p/1080i/1080p Y/C data.
– A single 24-bit YCbCr component or raw RGB data.
– Up to 2-stream multiplexed HD (720p/1080i) Y/C data.
– Up to 4-stream multiplexed ED (480p) Y/C data.
– Up to 8-stream multiplexed SD (480i) Y/C data.
– Up to 8-stream multiplexed CIF Y/C data.
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The video capture port channel supports de-multiplexing of both pixel-to-pixel and line-to-line
multiplexed streams.
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Up to 1920x1200@60Hz (160MHz) input data rate supports 16bit mode input port.
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Each video capture port supports one scaler capable of both up and down scaling of one
non-multiplexed input stream (one of two 8-bit channel inputs or 16-bit input channel input data). Note
that only down scaling is supported if the source is the VIN_PARSER or if the data path includes a
VENC.
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Each video capture port supports one programmable color space conversion to convert 24-bit RGB
data to YCbCr data.
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The HDVPSS supports data storage in 444, 422, and 420 formats.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
HD Video Processing Subsystem (HDVPSS)
Chip Level Resources
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