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1.5.3.2
SGX Elements Description
The coarse grain scheduler (CGS) is the main system controller for the POWERVR SGX architecture. It
consists of two stages, the DMS and the PDS. The DMS processes requests from the data masters and
determines which tasks can be executed given the resource requirements. The PDS then controls the
loading and processing of data on the USSE.
There are three data masters in the SGX core:
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The VDM is the initiator of transform and lighting processing within the system. The VDM reads an
input control stream, which contains triangle index data and state data. The state data indicates the
PDS program, size of the vertices, and the amount of USSE output buffer resource available to the
VDM. The triangle data is parsed to determine unique indices that must be processed by the USSE.
These are grouped together according to the configuration provided by the driver and presented to the
DMS.
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The PDM is the initiator of rasterization processing within the system. Each pixel pipeline processes
pixels for a different half of a given tile, which allows for optimum efficiency within each pipe due to
locality of data. It determines the amount of resource required within the USSE for each task. It merges
this with the state address and issues a request to the DMS for execution on the USSE.
•
The general-purpose data master responds to events within the system (such as end of a pass of
triangles from the ISP, end of a tile from the ISP, end of render, or parameter stream breakpoint
event). Each event causes either an interrupt to the host or synchronized execution of a program on
the PDS. The program may, or may not cause a subsequent task to be executed on the USSE.
The USSE is a user-programmable processing unit. Although general in nature, its instructions and
features are optimized for three types of task: processing vertices (vertex shading), processing pixels
(pixel shading), and video/imaging processing.
The multilevel cache is a 2-level cache consisting of two modules: the main cache and the
mux/arbiter/demux/decompression unit (MADD). The MADD is a wrapper around the main cache module
designed to manage and format requests to and from the cache, as well as providing Level 0 caching for
texture and USSE requests. The MADD can accept requests from the PDS, USSE, and texture address
generator modules. Arbitration, as well as any required texture decompression, are performed between
the three data streams.
The texturing coprocessor performs texture address generation and formatting of texture data. It receives
requests from either the iterators or USSE modules and translates these into requests in the multilevel
cache. Data returned from the cache are then formatted according to the texture format selected, and sent
to the USSE for pixel-shading operations.
To process pixels in a tiled manner, the screen is divided into tiles and arranged as groups of tiles by the
tiling coprocessor. An inherent advantage of tiling architecture is that a large amount of vertex data can be
rejected at this stage, thus reducing the memory storage requirements and the amount of pixel processing
to be performed.
The pixel coprocessor is the final stage of the pixel-processing pipeline and controls the format of the final
pixel data sent to the memory. It supplies the USSE with an address into the output buffer and then USSE
returns the relevant pixel data. The address order is determined by the frame buffer mode. The pixel
coprocessor contains a dithering and packing function.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
SGX530 Graphics Subsystem
151
Chip Level Resources
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