Texas Instruments TMS320C6A816 Series Technical Reference Manual page 29

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3-71. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP)
3-72. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP)
3-73. Transmit Channel n Completion Pointer Register (TXnCP)
3-74. Receive Channel n Completion Pointer Register (RXnCP)
3-75. Statistics Register
3-76. MDIO Version Register (VERSION)
3-77. MDIO Control Register (CONTROL)
3-78. PHY Acknowledge Status Register (ALIVE)
3-79. PHY Link Status Register (LINK)
3-80. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)
3-81. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
3-82. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)
3-83. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
3-84. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
3-85. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
3-86. MDIO User Access Register 0 (USERACCESS0)
3-87. MDIO User PHY Select Register 0 (USERPHYSEL0)
3-88. MDIO User Access Register 1 (USERACCESS1)
3-89. MDIO User PHY Select Register 1 (USERPHYSEL1)
4-1. GPIO Block Diagram
4-2. Synchronous Path Block Diagram
4-3. Interrupt Request Generation
4-4. Write @ GPIO_CLEARDATAOUT Register Example
4-5. Write @ GPIO_SETIRQENABLEx Register Example
4-6. General-Purpose Interface Used as a Keyboard Interface
4-7. GPIO_REVISION Register
4-8. GPIO_SYSCONFIG Register
4-9. GPIO_EOI Register
4-10. GPIO_IRQSTATUS_RAW_n Register
4-11. GPIO_IRQSTATUS_n Register
4-12. GPIO_IRQSTATUS_SET_n Register
4-13. GPIO_IRQSTATUS_CLR_n Register
4-14. GPIO_SYSSTATUS Register
4-15. GPIO_CTRL Register
4-16. GPIO_OE Register
4-17. GPIO_DATAIN Register
4-18. GPIO_DATAOUT Register
4-19. GPIO_LEVELDETECT0 Register
4-20. GPIO_LEVELDETECT1 Register
4-21. GPIO_RISINGDETECT Register
4-22. GPIO_FALLINGDETECT Register
4-23. GPIO_DEBOUNCENABLE Register
4-24. GPIO_DEBOUNCINGTIME Register
4-25. GPIO_CLEARDATAOUT Register
4-26. GPIO_SETDATAOUT Register
5-1. GPMC Block Diagram
5-2. GPMC to 16-Bit Address/Data-Multiplexed Memory
5-3. GPMC to 16-Bit Nonmultiplexed Memory
5-4. GPMC to 8-Bit NAND Device
SPRUGX9 - 15 April 2011
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© 2011, Texas Instruments Incorporated
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List of Figures