Texas Instruments TMS320C6A816 Series Technical Reference Manual page 172

Device Interrupts
MPUSS Interrupt Number
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
172 Chip Level Resources
Preliminary
Table 1-63. Cortex-A8 MPU INTC Interrupt Mapping (continued)
Event
MACRXINT0
MACTXINT0
MACMISC0
MACRXTHR1
MACRXINT1
MACTXINT1
MACMISC1
PCIINT0
PCIINT1
PCIINT2
PCIINT3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SDINT
SPIINT
Reserved
TINT1
TINT2
TINT3
I2CINT0
I2CINT1
UARTINT0
UARTINT1
UARTINT2
RTCINT
RTCALARMINT
MBINT
Reserved
Reserved
MCATXINT0
MCARXINT0
MCATXINT1
MCARXINT1
MCATXINT2
MCARXINT2
MCBSPINT
© 2011, Texas Instruments Incorporated
Interrupt Source Description
CPGMAC0 CPGMAC0 Receive pending interrupt
CPGMAC0 CPGMAC0 Transmit pending interrupt
CPGMAC0 CPGMAC0 Stat, Host, MDIO LINKINT or
MDIO USERINT
CPGMAC1 CPGMAC1 Receive threshold interrupt
CPGMAC1 CPGMAC1 Receive pending interrupt
CPGMAC1 CPGMAC1 Transmit pending interrupt
CPGMAC1 CPGMAC1 Stat, Host, MDIO LINKINT or
MDIO USERINT
PCIe Legacy Interrupts (RC mode only)
PCIe MSI Interrupts (RC mode only)
PCIe Error Interrupts
PCIe Power Management Interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SD/SDIO SDIO interrupt
McSPI SPI Interrupt
Reserved
Timer1 Timer 1 interrupt
Timer2 Timer 2 interrupt
Timer3 Timer 3 interrupt
I2C0 I2C0 interrupt
I2C1 I2C0 interrupt
UART0 UART/IrDA 0 interrupt
UART1 UART/IrDA 1 interrupt
UART2 UART/IrDA 2 interrupt
RTC Timer Interrupt
RTC Alarm interrupt
Mailbox Mailbox interrupt
Reserved
Reserved
McASP0 McASP 0 Transmit interrupt
McASP0 McASP 0 Receive interrupt
McASP1 McASP 1 Transmit interrupt
McASP1 McASP 1 Receive interrupt
McASP2 McASP 2 Transmit interrupt
McASP2 McASP 2 Receive interrupt
McBSP McBSP Common(TX/RX) Interrupt
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SPRUGX9 – 15 April 2011
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