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DSP Interrupt Number
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
SPRUGX9 – 15 April 2011
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Preliminary
Table 1-65. DSP INTC Interrupt Mapping (continued)
Event
HDVPSSINT
HDMIINT
Reserved
Reserved
Reserved
Reserved
Reserved
WDTINT
Reserved
TINT1
TINT2
TINT3
TINT4
TINT5
TINT6
TINT7
MBINT
Reserved
I2CINT0
I2CINT1
UARTINT0
UARTINT1
UARTINT2
Reserved
GPIOINT0A
GPIOINT0B
GPIOINT1A
GPIOINT1B
Reserved
Reserved
MCATXINT0
MCARXINT0
MCATXINT1
MCARXINT1
MCATXINT2
MCARXINT2
MCBSPINT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
© 2011, Texas Instruments Incorporated
Interrupt Source
Description
HD-VPSS
HD-VPSS Interrupt
HDMI
HDMI Interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
WDTIMER1
Watchdog Timer interrupt
Reserved
Timer1
Timer 1 interrupt
Timer2
Timer 2 interrupt
Timer3
Timer 3 interrupt
Timer4
Timer 4 interrupt
Timer5
Timer 5 interrupt
Timer6
Timer 6 interrupt
Timer7
Timer 7 interrupt
Mailbox
Mail Box Interrupt
Reserved
I2C0
I2C0 interrupt
I2C1
I2C0 interrupt
UART0
UART/IrDA 0 interrupt
UART1
UART/IrDA 1 interrupt
UART2
UART/IrDA 2 interrupt
Reserved
GPIO 0
GPIO 0 interrupt 1
GPIO 0
GPIO 0 interrupt 2
GPIO 1
GPIO 1 interrupt 1
GPIO 1
GPIO 1 interrupt 2
Reserved
Reserved
McASP0
McASP 0 Transmit interrupt
McASP0
McASP 0 Receive interrupt
McASP1
McASP 1 Transmit interrupt
McASP1
McASP 1 Receive interrupt
McASP2
McASP 2 Transmit interrupt
McASP2
McASP 2 Receive interrupt
McBSP
McBSP Common(TX/RX) Interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Device Interrupts
177
Chip Level Resources
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