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To Enable the SGX Functional and Interface Clock
Program the PRCM.CM_SGX_CLKSTCTRL.CTLKTRCTRL to 0x2
Program the PRCM.CM_SGX_SGX_CLKCTRL.MODULEMODE to 0x2
Poll for the PRCM.CM_SGX_SGX_CLKCTRL IDLEST to be 0x0
To Disable the SGX Functional and Interface Clock
Program the PRCM.CM_SGX_SGX_CLKCTRL.MODULEMODE to 0x0
Program the PRCM.CM_SGX_CLKSTCTRL.CTLKTRCTRL to 0x0
The SGX_ICLK and SGX_FLCK are sourced from SYSCLK23 Depending on the FAPLL and the
PRCM.CM_SYSCLK23_CLKSEL[CLKSEL] settings, SGX can support a frequency up to 333 MHz.
1.5.2.1.2 Resets
The SGX subsystem has its own reset domain. Global reset of the SGX is performed by activating the
SGX_RST signal in the SGX_RST domain. Software controls the release of SGX_RST using the
PRCM.RM_SGX_RSTCTRL[0] SGX_RST bit.
1.5.2.1.3 Power Management
The SGX subsystem has its own power domain (SGX power domain). See the Power, Reset, and Clock
Management chapter for additional information about the SGX power domain.
As described in the SGX Integration chapter, the SGX subsystem receives two clock signals from the
PRCM module. The functional clock is used inside the SGX to generate clock signals to the multiple
internal module SGX clock domains. The division ratio depends on the PRCM registers setting. For more
information, see the Power, Reset, and Clock Management chapter.
Three power-management modes are defined:
•
Deep power sleep (All clocks are gated.)
•
Idle (2D and 3D clocks are gated.)
•
3D (No clock is gated.)
The SGX handles the automatic clock gating performed on the multiple internal module clock domains.
1.5.2.2
Hardware Requests
1.5.2.2.1 Interrupt Request
The SGX subsystem can generate one interrupt (SGX_IRQ) to the MPU subsystem interrupt controller
mapped on M_IRQ_37.
SPRUGX9 – 15 April 2011
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© 2011, Texas Instruments Incorporated
SGX530 Graphics Subsystem
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