Texas Instruments TMS320C6A816 Series Technical Reference Manual page 168

C6-integra dsp+arm processors
Table of Contents

Advertisement

HD Video Processing Subsystem (HDVPSS)
Graphics Features
Three independently generated region-based graphics layers are supported.
Each graphics layer supports full-screen resolution graphics.
Each of the graphics pipelines includes an up/down scaler optimized for graphics application. The
scaler supports scaling ratios from 0.25× to 4× with 0.01 scaling step size.
Scaling of individual regions within a graphics layer is supported subject to other restrictions mentioned
later in this document. Note that regions are rectangular.
Supported Graphics formats are:
– 32-bit: ARGB8888.
– 24-bit: RGB888.
– 16-bit: ARGB1555, RGB565, ARGB4444.
– Bitmap: 1,2,4, 8-bit CLUT table.
– Multiple regions in a graphics layer are supported to reduce the amount of data transfer from the
external memory.
– Global and pixel-level alpha blending value is supported (256 levels). For pixel-level blending, the
alpha value can come from either source or CLUT table.
– Color keying (transparency) is supported.
– Stenciling (pixel masking with a separate 1-bit mask plane) is supported independently for each
graphics layer.
HD/SD Compositor Features
Three independently controlled compositors (HDMI/DVO1, HD-Comp, DVO2, SD) are supported to
drive the corresponding display encoder outputs.
The HD compositors supports composition of video and graphics layers to provide full size video
display, graphics overlay, video-in-graphics and picture-in-picture modes for HD video outputs.
The SD compositor supports video display, graphics overlay, and video-in-graphics for SD video
outputs.
Each input layer is given a display order priority which determines the display and blending orders.
Each output supports independent layer visibility control.
The compositor supports 256-level alpha blending of two overlapping layers.
The compositor supports display outputs to component and HDMI at different scan rates or different
pixel resolutions in addition to the separate SD output. VOUT0 must share either the HDMI or
component pixel clock.
HD/SD Video Signal Encoding Features (Video Displays)
A single HDMI 1.3 compliant interface with HDCP to support 1080p (1080p 24, 30, and 60 are
mandatory), 1080i, 720p, 480p, 480i. 640 × 480, 800 × 600, 1024 × 768, 1280 × 768, and
1920 × 1200.
Two VOUT interfaces that support up to 1080p@60 150MHz 8/16/24 YCbCr/RGB formats are
included. Each VOUT port supports both embedded and separated sync outputs. VBI data insertions
on VOUT outputs are not required.
HD Component: meets all requirements defined in ITU-R BT.470-6.
SD Composite/S-video (NTSC/PAL) meet all requirements defined in ITU-R BT.476-6 (TBD: SECAM
support).
SD SCART analog outputs.
4 MHz band limited NTSC Modulator interface.
All video outputs (Composite, S-Video, Component and HDMI) may be active simultaneously. The
HDMI and HD Component are in the same scan rate and pixel resolution except when the HDMI is
either in 1080p60 or 1920 × 1200 mode. If the HDMI is in 1080p60 mode, the HD Component displays
the HDMI output content in 1080i60 mode by interlacing the 1080p60 output. If the HDMI is in
1920 × 1200 mode, the HD Component defaults to 480i output mode.
Supported resolutions are 480i, 480p, 720p, 1080i, 1080p. Note that the maximum supported line width
is 1920 pixels. Furthermore, width and height values must always be an even number.
168
Chip Level Resources
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
Submit Documentation Feedback

Advertisement

Table of Contents
loading

Table of Contents