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5.5.10 GPMC_STATUS
5.5.11 GPMC_CONFIG1_i
5.5.12 GPMC_CONFIG2_i
5.5.13 GPMC_CONFIG3_i
5.5.14 GPMC_CONFIG4_i
5.5.15 GPMC_CONFIG5_i
5.5.16 GPMC_CONFIG6_i
5.5.17 GPMC_CONFIG7_i
5.5.18 GPMC_NAND_COMMAND_i
5.5.19 GPMC_NAND_ADDRESS_i
5.5.20 GPMC_NAND_DATA_i
5.5.21 GPMC_PREFETCH_CONFIG1
5.5.22 GPMC_PREFETCH_CONFIG2
5.5.23 GPMC_PREFETCH_CONTROL
5.5.24 GPMC_PREFETCH_STATUS
5.5.25 GPMC_ECC_CONFIG
5.5.26 GPMC_ECC_CONTROL
5.5.27 GPMC_ECC_SIZE_CONFIG
5.5.28 GPMC_ECCj_RESULT
5.5.29 GPMC_BCH_RESULT0_i
5.5.30 GPMC_BCH_RESULT1_i
5.5.31 GPMC_BCH_RESULT2_i
5.5.32 GPMC_BCH_RESULT3_i
5.5.33 GPMC_BCH_SWDATA
5.5.34 GPMC_BCH_RESULT4_i
5.5.35 GPMC_BCH_RESULT5_i
5.5.36 GPMC_BCH_RESULT6_i
6
High-Definition Multimedia Interface (HDMI)
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6.1
Introduction
6.1.1
Overview
6.1.2
Main Features
6.1.3
Functional Block Diagram
6.1.4
Video Formats and Timings
6.1.5
Environment
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6.2
Architecture
6.2.1
Clock Configuration
6.2.2
Signals
6.2.3
Integration
6.2.4
Software Reset
6.2.5
Power Management
6.2.6
Interrupt Requests
6.2.7
DMA Requests
6.2.8
HDCP Key Interface
6.2.9
Wrapper Functions
6.2.10 TXPHY Functions
6.2.11 Programming Video Input Mode and Video Output Mode
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6.3
Registers
6.3.1
HDMI_WP Register Descriptions
6.3.2
HDMI_IP_CORE_SYSTEM Register Descriptions
6.3.3
HDMI_IP_CORE_GAMUT Register Descriptions
6.3.4
HDMI_IP_CORE_AUDIO_VIDEO Register Descriptions
6.3.5
HDMI_IP_CORE_CEC Register Descriptions
6.3.6
HDMI_PHY Register Descriptions
SPRUGX9 – 15 April 2011
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