Table of Contents
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10.3.38 DIT Right Channel Status Registers (DITCSRB0-DITCSRB5)
10.3.39 DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5)
10.3.40 DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5)
10.3.41 Transmit Buffer Registers (XBUFn)
10.3.42 Receive Buffer Registers (RBUFn)
10.3.43 Write FIFO Control Register (WFIFOCTL)
10.3.44 Write FIFO Status Register (WFIFOSTS)
10.3.45 Read FIFO Control Register (RFIFOCTL)
10.3.46 Read FIFO Status Register (RFIFOSTS)
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Multichannel Buffered Serial Port (McBSP)
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11.1
Introduction
11.1.1 Overview
11.1.2 Features
11.1.3 Block Diagram
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11.2
Architecture
11.2.1 McBSP Data Transfer Process
11.2.2 McBSP Sample Rate Generator
11.2.3 McBSP Exception/Error Conditions
11.2.4 McBSP DMA Configuration
11.2.5 Multichannel Selection Modes
11.2.6 McBSP Full/Half Cycle Modes
11.2.7 Power Management
11.2.8 Programming Model
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11.3
Registers
11.3.1 McBSP Data Receive Register (DRR_REG)
11.3.2 McBSP Data Transmit Register (DXR_REG)
11.3.3 McBSP Serial Port Control Register 2 (SPCR2_REG)
11.3.4 McBSP Serial Port Control Register 1 (SPCR1_REG)
11.3.5 McBSP Receive Control Register 2 (RCR2_REG)
11.3.6 McBSP Receive Control Register 1 (RCR1_REG
11.3.7 McBSP Transmit Control Register 2 (XCR2_REG)
11.3.8 McBSP Transmit Control Register 1 (XCR1_REG)
11.3.9 McBSP Sample Rate Generator Register 2 (SRGR2_REG)
11.3.10 McBSP Sample Rate Generator Register 1 (SRGR1_REG)
11.3.11 McBSP Multichannel Register 2 (MCR2_REG)
11.3.12 McBSP Multichannel Register 1 (MCR1_REG)
11.3.13 McBSP Receive Channel Enable Register Partition A (RCERA_REG)
11.3.14 McBSP Receive Channel Enable Register Partition B (RCERB_REG)
11.3.15 McBSP Transmit Channel Enable Register Partition A (XCERA_REG)
11.3.16 McBSP Transmit Channel Enable Register Partition B (XCERB_REG)
11.3.17 McBSP Pin Control Register (PCR_REG)
11.3.18 McBSP Receive Channel Enable Register Partition C (RCERC_REG)
11.3.19 McBSP Receive Channel Enable Register Partition D (RCERD_REG)
11.3.20 McBSP Transmit Channel Enable Register Partition C (XCERC_REG)
11.3.21 McBSP Transmit Channel Enable Register Partition D (XCERD_REG)
11.3.22 McBSP Receive Channel Enable Register Partition E (RCERE_REG)
11.3.23 McBSP Receive Channel Enable Register Partition F (RCERF_REG)
11.3.24 McBSP Transmit Channel Enable Register Partition E (XCERE_REG)
11.3.25 McBSP Transmit Channel Enable Register Partition F (XCERF_REG)
11.3.26 McBSP Receive Channel Enable Register Partition G (RCERG_REG)
11.3.27 McBSP Receive Channel Enable Register Partition H (RCERH_REG)
11.3.28 McBSP Transmit Channel Enable Register Partition G (XCERG_REG)
11.3.29 McBSP Transmit Channel Enable Register Partition H (XCERH_REG)
12
Contents
Preliminary
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© 2011, Texas Instruments Incorporated
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SPRUGX9 – 15 April 2011
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