1.5.4 Sgx Registers; Sgx Registers Mapping Summary - Texas Instruments TMS320C6A816 Series Technical Reference Manual

SGX530 Graphics Subsystem

1.5.4 SGX Registers

All SGX registers are limited to 32-bit data accesses, 8- and 16-bit accesses
are not allowed because they can corrupt register content.
1.5.4.1 SGX OCP Register Summary
Offset Acronym
FE00h OCP_REVISION
FE04h OCP_HWINFO
FE10h OCP_SYSCONFIG
FE24h OCP_IRQSTATUS_RAW_0
FE28h OCP_IRQSTATUS_RAW_1
FE2Ch OCP_IRQSTATUS_RAW_2
FE30h OCP_IRQSTATUS_0
FE34h OCP_IRQSTATUS_1
FE38h OCP_IRQSTATUS_2
FE3Ch OCP_IRQENABLE_SET_0
FE40h OCP_IRQENABLE_SET_1
FE44h OCP_IRQENABLE_SET_2
FE48h OCP_IRQENABLE_CLR_0
FE4Ch OCP_IRQENABLE_CLR_1
FE50h OCP_IRQENABLE_CLR_2
FF00h OCP_PAGE_CONFIG
FF04h OCP_INTERRUPT_EVENT
FF08h OCP_DEBUG_CONFIG
FF0Ch OCP_DEBUG_STATUS
152
Chip Level Resources
Preliminary
CAUTION
Table 1-43. SGX Registers Mapping Summary
Register Description
OCP Revision Register
Hardware Implementation Information Register
System Configuration Register
Raw IRQ 0 Status Register
Raw IRQ 1 Status Register
Raw IRQ 2 Status Register
Interrupt 0 Status Event Register
Interrupt 1 Status Event Register
Interrupt 2 Status Event Register
Enable Interrupt 0 Register
Enable Interrupt 1 Register
Enable Interrupt 2 Register
Disable Interrupt 0 Register
Disable Interrupt 1 Register
Disable Interrupt 2 Register
Configure Memory Page Register
Interrupt Events Register
Configuration of Debug Modes Register
Debug Status Register
© 2011, Texas Instruments Incorporated
www.ti.com
Section
Section 1.5.4.1.1
Section 1.5.4.1.2
Section 1.5.4.1.3
Section 1.5.4.1.4
Section 1.5.4.1.5
Section 1.5.4.1.6
Section 1.5.4.1.7
Section 1.5.4.1.8
Section 1.5.4.1.9
Section 1.5.4.1.10
Section 1.5.4.1.11
Section 1.5.4.1.12
Section 1.5.4.1.13
Section 1.5.4.1.14
Section 1.5.4.1.15
Section 1.5.4.1.16
Section 1.5.4.1.17
Section 1.5.4.1.18
Section 1.5.4.1.19
SPRUGX9 – 15 April 2011
Submit Documentation Feedback