Table of Contents
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7
Inter-Integrated Circuit (I2C) Controller Module
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7.1
Introduction
7.1.1
Overview
7.1.2
Functional Block Diagram
7.1.3
Features
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7.2
Architecture
7.2.1
I2C Master/Slave Contoller Signals
7.2.2
I2C Reset
7.2.3
Data Validity
7.2.4
START & STOP Conditions
7.2.5
I2C Operation
7.2.6
Arbitration
7.2.7
I2C Clock Generation and I2C Clock Synchronization
7.2.8
Prescaler (SCLK/ICLK)
7.2.9
Noise Filter
7.2.10 I2C Interrupts
7.2.11 DMA Events
7.2.12 Interrupt and DMA Events
7.2.13 FIFO Management
7.2.14 How to Program I2C
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7.3
Registers
7.3.1
Module Revision Register (LOW BYTES) (I2C_REVNB_LO)
7.3.2
Module Revision Register (HIGH BYTES) (I2C_REVNB_HI)
7.3.3
System Configuration Register (I2C_SYSC)
7.3.4
I2C End of Interrupt Register (I2C_EOI)
7.3.5
I2C Status Raw Register (I2C_IRQSTATUS_RAW)
7.3.6
I2C Status Register (I2C_IRQSTATUS)
7.3.7
I2C Interrupt Enable Set Register (I2C_IRQENABLE_SET)
7.3.8
I2C Interrupt Enable Clear Register (I2C_IRQENABLE_CLR)
7.3.9
I2C Wakeup Enable Register (I2C_WE)
7.3.10 Receive DMA Enable Set Register (I2C_DMARXENABLE_SET)
7.3.11 Transmit DMA Enable Set Register (I2C_DMATXENABLE_SET)
7.3.12 Receive DMA Enable Clear Register (I2C_DMARXENABLE_CLR)
7.3.13 Transmit DMA Enable Clear Register (I2C_DMATXENABLE_CLR)
7.3.14 Receive DMA Wakeup Register (I2C_DMARXWAKE_EN)
7.3.15 Transmit DMA Wakeup Register (I2C_DMATXWAKE_EN)
7.3.16 System Status Register (I2C_SYSS)
7.3.17 Buffer Configuration Register (I2C_BUF)
7.3.18 Data Counter Register (I2C_CNT)
7.3.19 Data Access Register (I2C_DATA)
7.3.20 I2C Configuration Register (I2C_CON)
7.3.21 I2C Own Address Register (I2C_OA)
7.3.22 I2C Slave Address Register (I2C_SA)
7.3.23 I2C Clock Prescaler Register (I2C_PSC)
7.3.24 I2C SCL Low Time Register (I2C_SCLL)
7.3.25 I2C SCL High Time Register (I2C_SCLH)
7.3.26 System Test Register (I2C_SYSTEST)
7.3.27 I2C Buffer Status Register (I2C_BUFSTAT)
7.3.28 Own Address 1 (OA1) (I2C_OA1)
7.3.29 I2C Own Address 2 Register (I2C_OA2)
7.3.30 I2C Own Address 3 Register (I2C_OA3)
7.3.31 Active Own Address Register (I2C_ACTOA)
7.3.32 I2C Clock Blocking Enable Register (I2C_SBLOCK)
8
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Preliminary
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© 2011, Texas Instruments Incorporated
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SPRUGX9 – 15 April 2011
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