Texas Instruments TMS320C6A816 Series Technical Reference Manual page 28

3-22. EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT)
3-23. EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT)
3-24. EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX)
3-25. EMAC Control Module Transmit Interrupts per Millisecond Register (CMTXINTMAX)
3-26. Transmit Identification and Version Register (TXIDVER)
3-27. Transmit Control Register (TXCONTROL)
3-28. Transmit Teardown Register (TXTEARDOWN)
3-29. Receive Identification and Version Register (RXIDVER)
3-30. Receive Control Register (RXCONTROL)
3-31. Receive Teardown Register (RXTEARDOWN)
3-32. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
3-33. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
3-34. Transmit Interrupt Mask Set Register (TXINTMASKSET)
3-35. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
3-36. MAC Input Vector Register (MACINVECTOR)
3-37. MAC End Of Interrupt Vector Register (MACEOIVECTOR)
3-38. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
3-39. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
3-40. Receive Interrupt Mask Set Register (RXINTMASKSET)
3-41. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
3-42. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
3-43. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
3-44. MAC Interrupt Mask Set Register (MACINTMASKSET)
3-45. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
3-46. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)
3-47. Receive Unicast Enable Set Register (RXUNICASTSET)
3-48. Receive Unicast Clear Register (RXUNICASTCLEAR)
3-49. Receive Maximum Length Register (RXMAXLEN)
3-50. Receive Buffer Offset Register (RXBUFFEROFFSET)
3-51. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
3-52. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH)
3-53. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER)
3-54. MAC Control Register (MACCONTROL)
3-55. MAC Status Register (MACSTATUS)
3-56. Emulation Control Register (EMCONTROL)
3-57. FIFO Control Register (FIFOCONTROL)
3-58. MAC Configuration Register (MACCONFIG)
3-59. Soft Reset Register (SOFTRESET)
3-60. MAC Source Address Low Bytes Register (MACSRCADDRLO)
3-61. MAC Source Address High Bytes Register (MACSRCADDRHI)
3-62. MAC Hash Address Register 1 (MACHASH1)
3-63. MAC Hash Address Register 2 (MACHASH2)
3-64. Back Off Random Number Generator Test Register (BOFFTEST)
3-65. Transmit Pacing Algorithm Test Register (TPACETEST)
3-66. Receive Pause Timer Register (RXPAUSE)
3-67. Transmit Pause Timer Register (TXPAUSE)
3-68. MAC Address Low Bytes Register (MACADDRLO)
3-69. MAC Address High Bytes Register (MACADDRHI)
3-70. MAC Index Register (MACINDEX)
28
List of Figures
Preliminary
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© 2011, Texas Instruments Incorporated
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SPRUGX9 - 15 April 2011
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