1.10.2 I/O Domains; External Peripheral Clock Sources - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Device Clocking and Flying Adder PLL

1.10.2 I/O Domains

The I/O domains refer to the frequencies of the peripherals that communicate through device pins. In
many cases, there are frequency requirements for a peripheral pin interface that are set by an outside
standard and must be met. It is not necessarily possible to obtain these frequencies from the on-chip clock
generation circuitry, so the frequencies must be obtained from external sources and are asynchronous to
the CPU frequency by definition.
Peripheral
DDR2
DDR3
MTS
EMAC
MDIO
HDVPSS
McASP
McBSP
SPI
GPMC
I2C
RTC
TIMER
HDMI
PCIe/SATA
SD/SDIO
MAINPLL, DDRPLL,
VIDEOPLL, AUDIOPLL
186
Chip Level Resources
Preliminary
Table 1-70 shows the external Peripheral Clock Sources.
Table 1-70. External Peripheral Clock Sources
I/O (External) Domain Clock Source Options
I/O Domain Clock Internal Clock Source
Frequency
333 to 533 MHz SYSCLK8
333 to 800 MHz SYSCLK8
27 MHz SYSCLK14, SYSCLK16
125 MHz SYSCLK24
25 MHz SYSCLK6
162 MHz SYSCLK13, SYSCLK15, VIN[0]A_CLK, VIN[0]B_CLK,VIN[1]A_CLK,
SYSCLK17
50 MHz SYSCLK20, SYSCLK21, MCA[0]_ACLKX, MCA[0]_AHCLKX,
SYSCLK22
50 MHz SYSCLK20, SYSCLK21, MCB_CLKS, MCB_CLKX, MCB_CLKR
SYSCLK22
48 MHz SYSCLK6
125 MHz SYSCLK6
up to 400 KHz SYSCLK6
32.768 KHz
50 MHz
48 MHz SYSCLK13, SYSCLK15,
SYSCLK17
100 MHz
48 MHz SYSCLK6
27 MHz
© 2011, Texas Instruments Incorporated
External Clock Source
MTSI_DLCK
EMAC[0]_TXCLK, EMAC[0]_RXCLK,
EMAC[1]_TXCLK, EMAC[1]_RXCLK
VIN[1]B_CLK
MCA[0]_ACLKR, MCA[0]_AHCLKR,
MCA[1]_ACLKX, MCA[1]_AHCLKX,
MCA[1]_ACLKR, MCA[1]_AHCLKR,
MCA[2]_ACLKX, MCA[2]_AHCLKX,
MCA[2]_ACLKR, MCA[2]_AHCLKR
SPI_SCLK
I2C[0]_SCL, I2C[1]_SCL
CLKIN32
TCLKIN
SERDES_CLKP, SERDES_CLKN
CLKIN1
SPRUGX9 – 15 April 2011
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