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Indexed primitive list support
– Bus mastered
•
Programmable vertex DMA
•
Render to texture:
– Including twiddled formats
– Auto MipMap generation
•
Multiple on-chip render targets (MRT).
Note: Performance is limited when the on-chip memory is not available.
1.5.1.3
Universal Scalable Shader Engine (USSE) – Key Features
The USSE is the engine core of the POWERVR SGX architecture and supports a broad range of
instructions.
•
Single programming model:
– Multithreaded with 16 simultaneous execution threads and up to 64 simultaneous data instances
– Zero-cost swapping in, and out, of threads
– Cached program execution model
– Dedicated pixel processing instructions
– Dedicated video encode/decode instructions
•
SIMD execution unit supporting operations in:
– 32-bit IEEE float
– 2-way 16-bit fixed point
– 4-way 8-bit integer
– 32-bit bit-wise (logical only)
•
Static and dynamic flow control:
– Subroutine calls
– Loops
– Conditional branches
– Zero-cost instruction predication
•
Procedural geometry:
– Allows generation of primitives
– Effective geometry compression
– High-order surface support
•
External data access:
– Permits reads from main memory using cache
– Permits writes to main memory
– Data fence facility
– Dependent texture reads
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
SGX530 Graphics Subsystem
147
Chip Level Resources
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