Texas Instruments TMS320C6A816 Series Technical Reference Manual page 32

6-15. Interrupt Disable Register (HDMI_WP_IRQENABLE_CLEAR)
6-16. Glitch Filter Register (HDMI_WP_DEBOUNCE)
6-17. Configuration of HDMI Wrapper Video Register (HDMI_WP_VIDEO_CFG)
6-18. Configuration of Clocks Register (HDMI_WP_CLK)
6-19. Audio Configuration in FIFO Register (HDMI_WP_AUDIO_CFG)
6-20. Audio Configuration of DMA Register (HDMI_WP_AUDIO_CFG2)
6-21. Audio FIFO Control Register (HDMI_WP_AUDIO_CTRL)
6-22. TX Data of FIFO Register (HDMI_WP_AUDIO_DATA)
6-23. Vendor ID Register (VND_IDL)
6-24. Vendor ID Register (VND_IDH)
6-25. Device IDL Register (DEV_IDL)
6-26. Device IDH Register (DEV_IDH)
6-27. Device Revision Register (DEV_REV)
6-28. Software Reset Register (SRST)
6-29. System Control Register 1 (SYS_CTRL1)
6-30. System Status Register (SYS_STAT)
6-31. System Control Register 3 (SYS_CTRL3)
6-32. Data Control Register (DCTL)
6-33. HDCP Control Register (HDCP_CTRL)
6-34. HDCP BKSV Register (BKSV__0-BKSV__4)
6-35. HDCP AN Register (AN__0-AN__7)
6-36. HDCP AKSV Register (AKSV__0-AKSV__4)
6-37. HDCP Ri1 Register (RI1)
6-38. HDCP Ri2 Register (RI2)
6-39. HDCP Ri 128 Compare Register (RI_128_COMP)
6-40. HDCP I Counter Register (I_CNT)
6-41. Ri Status Register (RI_STAT)
6-42. Ri Command Register (RI_CMD)
6-43. Ri Line Start Register (RI_START)
6-44. Ri From RX Registers (Low) (RI_RX_L)
6-45. Ri From RX Registers (High) (RI_RX_H)
6-46. Ri Debug Registers (RI_DEBUG)
6-47. VIDEO DE Delay Register (DE_DLY)
6-48. VIDEO DE Control Register (DE_CTRL)
6-49. VIDEO DE Top Register (DE_TOP)
6-50. VIDEO DE Count Register (DE_CNTL)
6-51. VIDEO DE Count Register (DE_CNTH)
6-52. VIDEO DE Line Register (DE_LINL)
6-53. VIDEO DE Line Register (DE_LINH_1)
6-54. Video H Resolution Register (HRES_L)
6-55. Video H Resolution Register (HRES_H)
6-56. Video V Resolution Register (VRES_L)
6-57. Video V Resolution Register (VRES_H)
6-58. Video Interlace Adjustment Register (IADJUST)
6-59. Video SYNC Polarity Detection Register (POL_DETECT)
6-60. Video Hbit to HSYNC Register (HBIT_2HSYNC1)
6-61. Video Hbit to HSYNC Register (HBIT_2HSYNC2)
6-62. Video Field2 HSYNC Offset Register (FLD2_HS_OFSTL)
6-63. Video Field2 HSYNC Offset Register (FLD2_HS_OFSTH)
32
List of Figures
Preliminary
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SPRUGX9 - 15 April 2011