Texas Instruments TMS320C6A816 Series Technical Reference Manual page 49

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17-18. Timer Trigger Register (TTGR)
17-19. Timer Write Posted Status Register (TWPS)
17-20. Timer Match Register (TMAR)
17-21. Timer Capture Register (TCAR1)
17-22. Timer Synchronous Interface Control Register (TSICR)
17-23. Timer Capture Register (TCAR2)
18-1. Watchdog Timer Block Diagram
18-2. 32-Bit Watchdog Timer Functional Block Diagram
18-3. Watchdog Timers General Functional View
18-4. WDT_WIDR Register
18-5. WDT_WDSC Register
18-6. WDT_WDST Register
18-7. WDT_WISR Register
18-8. WDT_WIER Register
18-9. WDT_WCLR Register
18-10. WDT_WCRR Register
18-11. WDT_WLDR Register
18-12. WDT_WTGR Register
18-13. WDT_WWPS Register
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18-14. WDT_WDLY
18-15. WDT_WSPR Register
18-16. WDT_WIRQSTATRAW Register
18-17. WIRQSTAT Register
18-18. WDT_WIRQENSET Register
18-19. WDT_WIRQENCLR Register
19-1. UART to UART Connection With Full Handshaking
19-2. UART Frame Data Format
19-3. UART IrDA to External IR Device
19-4. IrDA SIR Frame Format
19-5. IrDA SIR Encoding Mechanism
19-6. IrDA SIR Decoding Mechanism
19-7. SIR Free Format Mode
19-8. MIR Transmit Frame Format
19-9. MIR Baud Rate Adjustment Mechanism
19-10. Serial Infrared Interaction Pulse (SIP)
19-11. RC-5 Bit Encoding
19-12. SIRC Bit Encoding
19-13. RC-5 Standard Packet Format
19-14. SIRC Packet Format
19-15. SIRC Bit Transmission Example
19-16. CIR Pulse Modulation
19-17. CIR Modulation Duty Cycle
19-18. FIFO Management
19-19. Receive FIFO Interrupt Request Generation
19-20. Transmit FIFO Interrupt Request Generation
19-21. Receive FIFO DMA Request Generation (32 Characters)
19-22. Transmit FIFO DMA Request Generation (56 Spaces)
19-23. Transmit FIFO DMA Request Generation (8 Spaces)
19-24. Transmit FIFO DMA Request Generation (1 Space)
SPRUGX9 - 15 April 2011
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© 2011, Texas Instruments Incorporated
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List of Figures