Texas Instruments TMS320C6A816 Series Technical Reference Manual page 56

1-1. MPU Subsystem Clock Frequencies
1-2. MPU Subsystem Clock Input Signals
1-3. Reset Scheme of the MPU Subsystem
1-4. ARM Core supported Features
1-5. Read Channel AXI ID to OCP Tag Mappings
1-6. Write Channel AXI ID to OCP Tag Mappings
1-7. Overview of the MPU Subsystem Power Domain
1-8. MPU Power States
1-9. MPU Subsystem Operation Power Modes
1-10. Address Map of the MPU Subsystem
1-11. First-Level Descriptor Format
1-12. Second-Level Descriptor Format
1-13. MMU Local Power Management Features
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1-14. Events
1-15. Error Handling
1-16. Configure a TLB Entry
1-17. MMU Writing TLB Entries Statically
1-18. Protecting TLB Entries
1-19. Deleting TLB Entries
1-20. Read TLB Entries
1-21. MMU Instance Summary
1-22. MMU Registers
1-23. MMU_REVISION Field Descriptions
1-24. MMU_SYSCONFIG Field Descriptions
1-25. MMU_SYSSTATUS Field Descriptions
1-26. MMU_IRQSTATUS Field Descriptions
1-27. MMU_IRQENABLE Field Descriptions
1-28. MMU_WALKING_ST Field Descriptions
1-29. MMU_CNTL Field Descriptions
1-30. MMU_FAULT_AD Field Descriptions
1-31. MMU_TTB Field Descriptions
1-32. MMU_LOCK Field Descriptions
1-33. MMU_LD_TLB Field Descriptions
1-34. MMU_CAM Field Descriptions
1-35. MMU_RAM Field Descriptions
1-36. MMU_GFLUSH Field Descriptions
1-37. MMU_FLUSH_ENTRY Field Descriptions
1-38. MMU_READ_CAM Field Descriptions
1-39. MMU_READ_RAM Field Descriptions
1-40. MMU_EMU_FAULT_AD Field Descriptions
1-41. MMU_FAULT_PC Field Descriptions
1-42. Clock Descriptions
1-43. SGX Registers Mapping Summary
1-44. OCP Revision Register (OCP_REVISION) Field Descriptions
1-45. Hardware Implementation Information Register (OCP_HWINFO) Field Descriptions
1-46. System Configuration Register (OCP_SYSCONFIG) Field Descriptions
1-47. Raw IRQ 0 Status Register (OCP_IRQSTATUS_RAW_0) Field Descriptions
56
List of Tables
Preliminary
List of Tables
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© 2011, Texas Instruments Incorporated
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SPRUGX9 - 15 April 2011
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