Texas Instruments TMS320C6A816 Series Technical Reference Manual page 73

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10-14. Pin Data Input Register (PDIN) Field Descriptions
10-15. Pin Data Set Register (PDSET) Field Descriptions
10-16. Pin Data Clear Register (PDCLR) Field Descriptions
10-17. Global Control Register (GBLCTL) Field Descriptions
10-18. Audio Mute Control Register (AMUTE) Field Descriptions
10-19. Digital Loopback Control Register (DLBCTL) Field Descriptions
10-20. Digital Mode Control Register (DITCTL) Field Descriptions
10-21. Receiver Global Control Register (RGBLCTL) Field Descriptions
10-22. Receive Format Unit Bit Mask Register (RMASK) Field Descriptions
10-23. Receive Bit Stream Format Register (RFMT) Field Descriptions
10-24. Receive Frame Sync Control Register (AFSRCTL) Field Descriptions
10-25. Receive Clock Control Register (ACLKRCTL) Field Descriptions
10-26. Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Descriptions
10-27. Receive TDM Time Slot Register (RTDM) Field Descriptions
10-28. Receiver Interrupt Control Register (RINTCTL) Field Descriptions
10-29. Receiver Status Register (RSTAT) Field Descriptions
10-30. Current Receive TDM Time Slot Registers (RSLOT) Field Descriptions
10-31. Receive Clock Check Control Register (RCLKCHK) Field Descriptions
10-32. Receiver DMA Event Control Register (REVTCTL) Field Descriptions
10-33. Transmitter Global Control Register (XGBLCTL) Field Descriptions
10-34. Transmit Format Unit Bit Mask Register (XMASK) Field Descriptions
10-35. Transmit Bit Stream Format Register (XFMT) Field Descriptions
10-36. Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions
10-37. Transmit Clock Control Register (ACLKXCTL) Field Descriptions
10-38. Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Descriptions
10-39. Transmit TDM Time Slot Register (XTDM) Field Descriptions
10-40. Transmitter Interrupt Control Register (XINTCTL) Field Descriptions
10-41. Transmitter Status Register (XSTAT) Field Descriptions
10-42. Current Transmit TDM Time Slot Register (XSLOT) Field Descriptions
10-43. Transmit Clock Check Control Register (XCLKCHK) Field Descriptions
10-44. Transmitter DMA Event Control Register (XEVTCTL) Field Descriptions
10-45. Serializer Control Registers (SRCTLn) Field Descriptions
10-46. Write FIFO Control Register (WFIFOCTL) Field Descriptions
10-47. Write FIFO Status Register (WFIFOSTS) Field Descriptions
10-48. Read FIFO Control Register (RFIFOCTL) Field Descriptions
10-49. Read FIFO Status Register (RFIFOSTS) Field Descriptions
11-1. Phases, Words and Bits Per Frame Control Bits
11-2. Effects of DLB and ALB Bits on Clock Modes
11-3. Channels, Block, Partitions
11-4. Eight Partitions - Receive Channel Assignment and Control
11-5. Eight Partitions - Transmit Channel Assignment and Control
11-6. Selecting a Transmit Multichannel Selection Mode with the XMCM Bit Field
11-7. McBSP Channel Control Options
11-8. Analysis of the Receiver Smart Idle Behavior
11-9. Input Clock Selection for Sample Rate Generator
11-10. How to Calculate the Length of the Receive Frame
11-11. Example: Use of RJUST Bit Field with 12-Bit Data Value ABCh
11-12. Example: Use of RJUST Bit Field with 20-Bit Data Value ABCDE
11-13. FSRM and GSYNC Effects on Frame-Sync Signal and McBSP.FSR Pin
SPRUGX9 - 15 April 2011
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© 2011, Texas Instruments Incorporated
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