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8
Interrupt Controller
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8.1
Introduction
8.1.1
Overview
8.1.2
Functional Block Diagram
8.1.3
Environment
8.1.4
ARM A8—Interrupt Controller Integration
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8.2
Architecture
8.2.1
Clocking and Reset
8.2.2
Interrupt Request Lines
8.2.3
Interrupt Processing
8.2.4
Module Power Saving
8.2.5
Error Handling
8.2.6
Interrupt Latency
8.3
Basic Programming Model
8.3.1
Initialization Sequence
8.3.2
INTC Processing Sequence
8.3.3
INTC Preemptive Processing Sequence
8.3.4
Interrupt Preemption
8.3.5
ARM A8 INTC Spurious Interrupt Handling
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8.4
Registers
8.4.1
INTCPS_REVISION Register
8.4.2
INTCPS_SYSCONFIG Register
8.4.3
INTCPS_SYSSTATUS Register
8.4.4
INTCPS_SIR_IRQ Register
8.4.5
INTCPS_SIR_FIQ Register
8.4.6
INTCPS_CONTROL Register
8.4.7
INTCPS_PROTECTION Register
8.4.8
INTCPS_IDLE Register
8.4.9
INTCPS_IRQ_PRIORITY Register
8.4.10 INTCPS_FIQ_PRIORITY Register
8.4.11 INTCPS_THRESHOLD Register
8.4.12 INTCPS_ITR0-3 Registers
8.4.13 INTCPS_MIR0-3 Registers
8.4.14 INTCPS_MIR_CLEAR0-3 Registers
8.4.15 INTCPS_MIR_SET0-3 Registers
8.4.16 INTCPS_ISR_SET0-3 Registers
8.4.17 INTCPS_ISR_CLEAR0-3 Registers
8.4.18 INTCPS_PENDING_IRQ0-3 Registers
8.4.19 INTCPS_PENDING_FIQ0-3 Registers
8.4.20 INTCPS_ILR0-127 Registers
9
Secure Digital (SD)/Secure Digital I/O (SDIO) Card Interface
...............................................................................................................
9.1
Introduction
9.1.1
Overview
9.1.2
Features
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9.2
Architecture
9.2.1
SD/SDIO Functional Modes
9.2.2
Resets
9.2.3
Power Management
9.2.4
Interrupt Requests
9.2.5
DMA Modes
9.2.6
Buffer Management
9.2.7
Transfer Process
9.2.8
Transfer or Command Status and Error Reporting
SPRUGX9 – 15 April 2011
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© 2011, Texas Instruments Incorporated
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