Supersection Translation Summary - Texas Instruments TMS320C6A816 Series Technical Reference Manual

C6-integra dsp+arm processors
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1.4.3.1.2.7 Supersection Translation Summary

The translation of a supersection is similar to the translation of a section. The difference is that for a
supersection only bits 31 to 24 index into the first-level translation table. The last four bits of the table
index are implicitly assumed to be zero as there are 16 identical consecutive entries for a supersection.
31
24 23
First-level translation table
SPRUGX9 – 15 April 2011
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Preliminary
Figure 1-18. Supersection Translation Summary
Virtual address
Supersection base address
(From first-level descriptor)
31
© 2011, Texas Instruments Incorporated
0
24 23
Physical address
System MMU
0
123
Chip Level Resources

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