Texas Instruments TMS320C6A816 Series Technical Reference Manual page 41

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12-14. Transmit/Receive Mode With Only Transmit FIFO Used
12-15. Transmit/Receive Mode With Both FIFO Direction Used
12-16. Transmit-Only Mode With FIFO Used
12-17. Receive-Only Mode With FIFO Used
12-18. Buffer Almost Full Level (AFL)
12-19. Buffer Almost Empty Level (AEL)
12-20. Master Single Channel Initial Delay
12-21. 3-Pin Mode System Overview
12-22. Example of SPI Slave with One Master and Multiple Slave Devices on Channel 0
12-23. SPI Half-Duplex Transmission (Receive-Only Slave)
12-24. SPI Half-Duplex Transmission (Transmit-Only Slave)
12-25. McSPI System Configuration Register (MCSPI_SYSCONFIG)
12-26. McSPI System Status Register (MCSPI_SYSSTATUS)
12-27. McSPI Interrupt Status Register (MCSPI_IRQSTATUS)
12-28. McSPI Interrupt Enable Register (MCSPI_IRQENABLE)
12-29. McSPI System Register (MCSPI_SYST)
12-30. McSPI Module Control Register (MCSPI_MODULCTRL)
12-31. McSPI Channel (i ) Configuration Register (MCSPI_CH(i)CONF)
12-32. McSPI Channel (i) Status Register (MCSPI_CH(i)STAT)
12-33. McSPI Channel (i) Control Register (MCSPI_CH(I)CTRL)
12-34. McSPI Channel (i) Transmit Register (MCSPI_TX(i))
12-35. McSPI Channel (i) Receive Register (MCSPI_RX(i))
12-36. McSPI Transfer Levels Register (MCSPI_XFERLEVEL)
13-1. PCIe Subsystem (PCIESS) Block Diagram
13-2. Outbound Address Translation
13-3. Address Space Zero Relationships
13-4. PCIe Configuration Register (PCIE_CFG)
13-5. PCIe Test Pattern Control Register (PCIE_TEST_CTRL)
13-6. RM_DEFAULT_RSTCTRL Register
13-7. RM_DEFAULT_RSTST Register
13-8. CM_DEFAULT_PCI_CLKSTCTRL Register
13-9. CM_DEFAULT_PCI_CLKCTRL Register
13-10. Device Power Management States
13-11. Transitions Between Link States
13-12. Link State Transition to L1 State
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13-13. PID Register
13-14. CMD_STATUS Register
13-15. CFG_SETUP Register
13-16. IOBASE Register
13-17. TLPCFG Register
13-18. RSTCMD Register
13-19. PMCMD Register
13-20. PMCFG Register
13-21. ACT_STATUS Register
13-22. OB_SIZE Register
13-23. DIAG_CTRL Register
13-24. ENDIAN Register
13-25. PRIORITY Register
13-26. IRQ_EOI Register
SPRUGX9 - 15 April 2011
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List of Figures