Texas Instruments TMS320C6A816 Series Technical Reference Manual page 36

8-15. INTCPS_FIQ_PRIORITY Register
8-16. INTCPS_THRESHOLD Register
8-17. INTCPS_ITRn Register
8-18. INTCPS_MIRn Register
8-19. INTCPS_MIR_CLEARn Register
8-20. INTCPS_MIR_SETn Register
8-21. INTCPS_ISR_SETn Register
8-22. INTCPS_ISR_CLEARn Register
8-23. INTCPS_PENDING_IRQn Register
8-24. INTCPS_PENDING_FIQn Register
8-25. INTCPS_ILRm Register
9-1. SD/SDIO1 Overview
9-2. SD1 Connectivity to an SD Card
9-3. Command Token Format
9-4. 48-Bit Response Packet (R1, R3, R4, R5, R6)
9-5. 136-Bit Response Packet (R2)
9-6. Data Packet for Sequential Transfer (1-Bit)
9-7. Data Packet for Block Transfer (1-Bit)
9-8. Data Packet for Block Transfer (4-Bit)
9-9. DMA Receive Mode
9-10. DMA Transmit Mode
9-11. Buffer Management for a Write
9-12. Buffer Management for a Read
9-13. Busy Timeout for R1b, R5b Responses
9-14. Busy Timeout After Write CRC Status
9-15. Write CRC Status Timeout
9-16. Read Data Timeout
9-17. Boot Acknowledge Timeout When Using CMD0
9-18. Boot Acknowledge Timeout When CMD Held Low
9-19. Auto CMD12 Timing During Write Transfer
9-20. Auto Command 12 Timings During Read Transfer
9-21. Output Driven on Falling Edge
9-22. Output Driven on Rising Edge
9-23. Boot Mode With CMD0
9-24. Boot Mode With CMD Line Tied to 0
9-25. SD/SDIO Controller Software Reset Flow
9-26. SD/SDIO Controller Bus Configuration Flow
9-27. SD/SDIO Controller Card Identification and Selection - Part 1
9-28. SD/SDIO Controller Card Identification and Selection - Part 2
9-29. SD_HL_REV Register
9-30. SD_HL_HWINFO Register
9-31. SD_HL_SYSCONFIG Register
9-32. System Configuration Register (SD_SYSCONFIG)
9-33. System Status Register (SD_SYSSTATUS)
9-34. Card Status Response Error (SD_CSRE)
9-35. System Test Register (SD_SYSTEST)
9-36. Configuration Register (SD_CON)
9-37. Power Counter Register (SD_PWCNT)
9-38. Card Status Response Error (SD_SDMASA)
36
List of Figures
Preliminary
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© 2011, Texas Instruments Incorporated
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SPRUGX9 - 15 April 2011
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