Texas Instruments TMS320C6A816 Series Technical Reference Manual page 34

6-113. xvYCC_2_RGB Conversion Y_2_R Register (Y2R_COEFF_UP)
6-114. xvYCC_2_RGB Conversion Cr_2_R Register (CR2R_COEFF_LOW)
6-115. xvYCC_2_RGB Conversion Cr_2_R Register (C2R2R_COEFF_UP)
6-116. xvYCC_2_RGB Conversion Cb_2_B Register (CB2B_COEFF_LOW)
6-117. xvYCC_2_RGB Conversion Cb_2_B Register (CB2B_COEFF_UP)
6-118. xvYCC_2_RGB Conversion Cr_2_G Register (CR2G_COEFF_LOW)
6-119. xvYCC_2_RGB Conversion Cr_2_G Register (CR2G_COEFF_UP)
6-120. xvYCC_2_RGB Conversion Cb_2_G Register (CB2G_COEFF_LOW)
6-121. xvYCC_2_RGB Conversion Cb_2_G Register (CB2G_COEFF_UP)
6-122. xvYCC_2_RGB Conversion Y Offset Register (YOFFSET1_LOW)
6-123. xvYCC_2_RGB Conversion Y Offset Register (YOFFSET1_UP)
6-124. xvYCC_2_RGB Conversion Offset1 Register (OFFSET1_LOW)
6-125. xvYCC_2_RGB Conversion Offset1 Register (OFFSET1_MID)
6-126. xvYCC_2_RGB Conversion Offset1 Register (OFFSET1_UP)
6-127. xvYCC_2_RGB Conversion Offset2 Register (OFFSET2_LOW)
6-128. xvYCC_2_RGB Conversion Offset2 Register (OFFSET2_UP)
6-129. xvYCC_2_RGB Conversion DC Level Register (DCLEVEL_LOW)
6-130. xvYCC_2_RGB Conversion DC Level Register (DCLEVEL_UP)
6-131. DDC I2C Manual Register (DDC_MAN)
6-132. DDC I2C Target Slave Address Register (DDC_ADDR)
6-133. DDC I2C Target Segment Address Register (DDC_SEGM)
6-134. DDC I2C Target Offset Address Register (DDC_OFFSET)
6-135. DDC I2C Data Count Register (DDC_COUNT1)
6-136. DDC I2C Data Count Register (DDC_COUNT2)
6-137. DDC I2C Status Register (DDC_STATUS)
6-138. DDC I2C Command Register (DDC_CMD)
6-139. DDC I2C Data Register (DDC_DATA)
6-140. DDC I2C FIFO Count Register (DDC_FIFOCNT)
6-141. ROM Status Register (EPST)
6-142. ROM Command Register (EPCM)
6-143. Gamut Metadata Register (GAMUT_HEADER1)
6-144. Gamut Metadata Register (GAMUT_HEADER2)
6-145. Gamut Metadata Register (GAMUT_HEADER3)
6-146. Gamut Metadata Registers (GAMUT_DBYTE__0-GAMUT_DBYTE__27)
6-147. ACR Control Register (ACR_CTRL)
6-148. ACR Audio Frequency Register (FREQ_SVAL)
6-149. ACR N Software Value Register (N_SVAL1)
6-150. ACR N Software Value Register (N_SVAL2)
7-1. I2C Functional Block Diagram
7-2. Multiple I2C Modules Connected
7-3. Bit Transfer on the I2C Bus
7-4. Start and Stop Condition Events
7-5. I2C Data Transfer
7-6. I2C Data Transfer Formats
7-7. Arbitration Procedure Between Two Master Transmitters
7-8. Synchronization of Two I2C Clock Generators
7-9. Receive FIFO Interrupt Request Generation
7-10. Transmit FIFO Interrupt Request Generation
7-11. Receive FIFO DMA Request Generation
34
List of Figures
Preliminary
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© 2011, Texas Instruments Incorporated
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SPRUGX9 - 15 April 2011
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