Table of Contents
Advertisement
www.ti.com
MPUSS Interrupt Number
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Preliminary
Table 1-63. Cortex-A8 MPU INTC Interrupt Mapping (continued)
Event
Reserved
Reserved
Reserved
Reserved
WDTINT
TINT4
TINT5
TINT6
TINT7
GPIOINT0A
GPIOINT0B
GPIOINT1A
GPIOINT1B
GPMCINT
DDRERR0
DDRERR1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TCERRINT0
TCERRINT1
TCERRINT2
TCERRINT3
Reserved
Reserved
Reserved
Reserved
SMRFLX0
SMRFLX1
SYSMMUINT
MCMMUINT
DMMINT
Reserved
Reserved
Reserved
© 2011, Texas Instruments Incorporated
Interrupt Source
Description
Reserved
Reserved
Reserved
Reserved
WDTIMER1
Watchdog Timer interrupt
Timer4
Timer 4 interrupt
Timer5
Timer 5 interrupt
Timer6
Timer 6 interrupt
Timer7
Timer 7 interrupt
GPIO 0
GPIO 0 interrupt 1
GPIO 0
GPIO 0 interrupt 2
GPIO 1
GPIO 1 interrupt 1
GPIO 1
GPIO 1 interrupt 2
GPMC
GPMC interrupt
DDR EMIF0
DDR2/3 0 Error interrupt
DDR EMIF1
DDR2/3 1 Error interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TPTC0
TPTC0 error interrupt
TPTC1
TPTC1 error interrupt
TPTC2
TPTC2 error interrupt
TPTC3
TPTC3 error interrupt
Reserved
Reserved
Reserved
Reserved
Smart Reflex0
SVT SmartReflex interrupt
Smart Reflex1
HVT SmartReflex interrupt
System MMU
Table walk abort interrupt
Media Controller
MMU Fault interrupt
DMM
PAT Fault interrupt
Reserved
Reserved
Reserved
Device Interrupts
173
Chip Level Resources
Advertisement
Table of Contents
