Texas Instruments TMS320C6A816 Series Technical Reference Manual page 236

Mailbox
Table 1-111. IRQ Enable Clear Register (MAILBOX_IRQENABLE_CLR_u) Field Descriptions (continued)
Bit Field
0 NEWMSGSTATUSUUM
B0
236
Chip Level Resources
Preliminary
Value Description
New Message Status bit for User u, Mailbox 0
0 Read: No event (message) pending
1 Read: Event (message) pending
0 Write: No action
1 Write: Set the event (for debug)
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SPRUGX9 – 15 April 2011
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