Texas Instruments TMS320C6A816 Series Technical Reference Manual page 228

Mailbox
Table 1-109. IRQ Clear Status Register (MAILBOX_IRQSTATUS_CLR_u) Field Descriptions (continued)
Bit Field
1 NOTFULLSTATUSUUM
B0
0 NEWMSGSTATUSUUM
B0
228
Chip Level Resources
Preliminary
Value Description
Not Full Status bit for User u, Mailbox 0
0 Read: No event pending (message queue full)
1 Read: Event pending (message queue not full)
0 Write: No action
1 Write: Set the event (for debug)
New Message Status bit for User u, Mailbox 0
0 Read: No event (message) pending
1 Read: Event (message) pending
0 Write: No action
1 Write: Set the event (for debug)
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SPRUGX9 – 15 April 2011
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