Texas Instruments TMS320C6A816 Series Technical Reference Manual page 22

1-1. Microprocessor Unit (MPU) Subsystem
1-2. MicroProcessor Unit (MPU) Subsystem Signal Interface
1-3. MPU Subsystem Clocking Scheme
1-4. Reset Scheme of the MPU Subsystem
1-5. Overview of the AXI2OCP and the L3 Bridges
1-6. MPU Subsystem Power Domain Overview
1-7. TMS320C674x Megamodule Block Diagram
1-8. DSP Subsystem Block Diagram
1-9. TMS320C674x Megamodule Block Diagram
1-10. DSP Megamodule INTC Block Diagram
1-11. Typical MMU Intergration
1-12. MMU Block Diagram
1-13. MMU Address Translation Process
1-14. Translation Hierarchy
1-15. First-Level Descriptor Address Calculation
1-16. Detailed First-Level Descriptor Address Calculation
1-17. Section Translation Summary
1-18. Supersection Translation Summary
1-19. Two-Level Translation
1-20. Small Page Translation Summary
1-21. Large Page Translation Summary
1-22. TLB-Entry Lock Mechanism
1-23. TLB-Entry Structure
1-24. MMU Global Initialization
1-25. MMU_REVISION
1-26. MMU_SYSCONFIG
1-27. MMU_SYSSTATUS
1-28. MMU_IRQSTATUS
1-29. MMU_IRQENABLE
1-30. MMU_WALKING_ST
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1-31. MMU_CNTL
1-32. MMU_FAULT_AD
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1-33. MMU_TTB
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1-34. MMU_LOCK
1-35. MMU_LD_TLB
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1-36. MMU_CAM
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1-37. MMU_RAM
1-38. MMU_GFLUSH
1-39. MMU_FLUSH_ENTRY
1-40. MMU_READ_CAM
1-41. MMU_READ_RAM
1-42. MMU_EMU_FAULT_AD
1-43. MMU_FAULT_PC
1-44. Graphics Accelerator Highlight
1-45. SGX Subsystem Integration
1-46. SGX Block Diagram
1-47. OCP Revision Register (OCP_REVISION)
22
List of Figures
Preliminary
List of Figures
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© 2011, Texas Instruments Incorporated
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SPRUGX9 - 15 April 2011
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