Tektronix AWG2021 User Manual page 537

Appendix E: Functional Operation Summary
Clock Divider
E 8
Trigger Input, SYNC Output, and Waveform Timing. Figure E-7 shows the
relationship between trigger input, SYNC output, and waveform timing.
Trigger Input
(Slope:Positive)
SYNC Output
(Start)
Waveform Output
Figure E 7: Trigger Input, SYNC Output, and Waveform Timing
The CH1 clock divider divides the clock signal from the clock oscillator the
amount necessary to obtain the frequency value indicated in the Clock box in the
SETUP menu. Division by up to 2
can have different division ratios. The CH2 clock divider (that is, CH2 clock
frequency) is set in the Divider box in the SETUP menu.
When an external clock source is selected, the CH1 clock divider does not
operate and the clock signals are just passed through, as is. However, the CH2
clock divider will still divide the external clock source based on the selected
ratio. Figure E-8 shows the configuration of a clock divider.
n/256
Figure E 8: Clock Divider Configuration
100 ns max
About 10 ns
(This delay changes if a filter is inserted.)
24
is possible, and the CH1 and CH2 dividers
n/256 n/256
n = 2  256
AWG2021 User Manual