R&S ESR Series User Manual page 591

®
R&S ESR
Bit No.
8
9
10
11
12
13 - 14
15
STATus:QUEStionable:ACPLimit Register
The STATus:QUEStionable:ACPLimit register contains information about the results of
a limit check during ACLR measurements.
You can read out the register with
or STATus:QUEStionable:ACPLimit[:EVENt]?.
Table 11-17: Meaning of the bits used in the STATus:QUEStionable:ACPLimit register
Bit No.
0
1
2
3
4
5
6
User Manual 1175.7068.02 ─ 12
Meaning
CALibration
This bit is set if the R&S ESR is unaligned ("UNCAL" display)
LIMit (device-specific)
This bit is set if a limit value is violated.
The STATus:QUEStionable:LIMit Register
LMARgin (device-specific)
This bit is set if a margin is violated.
The STATus:QUEStionable:LMARgin Register
Not used
ACPLimit (device-specific)
This bit is set if a limit during ACLR measurements is violated.
The STATus:QUEStionable:ACPLimit Register
Not used
This bit is always 0.
Meaning
ADJ UPPer FAIL
This bit is set if the limit is exceeded in the upper adjacent channel
ADJ LOWer FAIL
This bit is set if the limit is exceeded in the lower adjacent channel.
ALT1 UPPer FAIL
This bit is set if the limit is exceeded in the upper 1st alternate channel.
ALT1 LOWer FAIL
This bit is set if the limit is exceeded in the lower 1st alternate channel.
ALT2 UPPer FAIL
This bit is set if the limit is exceeded in the upper 2nd alternate channel.
ALT2 LOWer FAIL
This bit is set if the limit is exceeded in the lower 2nd alternate channel.
ALT3 ... 11 LOWer/UPPer FAIL
This bit is set if the limit is exceeded in one of the lower or upper alternate channels 3 ... 11.
provides more information on the error type.
provides more information on the error type.
provides more information on the error type.
STATus:QUEStionable:ACPLimit:CONDition?
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